VHDL example code

This project contains chunks of example VHDL source code, distributed as educational material under the MIT License and written by Brian Nezvadovitz.

What's in the box?

Simple Examples

• adders_1bit - 1-bit half-adder and 1-bit full-adder examples demonstate the use of combinatorial logic

• multiplexer - 2:1 and 4:1 multiplexer examples demonstrate the use of generics in purely combinatorial code

• adder_numeric_std - Basic use of the numeric_std library is shown with a full adder of generic width

• decoder - A binary to one-hot decoder with enable signal demonstrates the use of the combinatorial process block

• register - Demonstration of the clocked process and the basic memory storage element

Intermediate Examples

• shift_reg - Shift register example demonstrates the simple use of generics and the single-process model

• clock_divider - Logic-only parameterized clock divider that uses a cycle counter in its implementation

• pulse_emitter - Emits single-cycle pulses at regular intervals when enabled; demonstrates use of 2-process model

Complex Examples

• adder_tree - Adder tree example demonstrates how to write recursive, pipelined VHDL