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@spider-tronix
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Pinned

  1. sachin-101/e-Yantra-Robotics-Competition sachin-101/e-Yantra-Robotics-Competition Public

    Tasks of eYRC 2019-20

    Python 1 2

  2. spider-tronix/VLSI spider-tronix/VLSI Public archive

    RISC V core implementation using Verilog.

    Verilog 23 4

  3. GauravSingh789/Cascaded-SVM-on-FPGA GauravSingh789/Cascaded-SVM-on-FPGA Public

    Implementing a cascaded SVM on FPGA

    Verilog 6 2