Skip to content

kitsuneh/SVGameBoy

master
Switch branches/tags

Name already in use

A tag already exists with the provided branch name. Many Git commands accept both tag and branch names, so creating this branch may cause unexpected behavior. Are you sure you want to create this branch?
Code

Latest commit

 

Git stats

Files

Permalink
Failed to load latest commit information.
Type
Name
Latest commit message
Commit time
 
 
RTL
 
 
 
 

SVGameBoy

A systemVerilog implementation of the Game Boy on DE1-SoC

This was for CSEE 4840 Embedded System Design @ Columbia University

To make target files for DE1-SoC make qsys && make quartus && make rbf

Accuracy

Blargg's tests

Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours
cpu instrs πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
dmg sound ❌ πŸ‘ N/A N/A N/A N/A ❌
instr timing πŸ‘ πŸ‘ N/A N/A N/A N/A πŸ‘
interrupt time N/A ❌ N/A N/A N/A N/A ❌
mem timing N/A πŸ‘ N/A N/A N/A N/A πŸ‘
mem timing 2 πŸ‘ πŸ‘ N/A N/A N/A N/A πŸ‘
oam bug ❌ ❌ N/A N/A N/A N/A ❌

Mooneye GB acceptance tests

Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours
add sp e timing πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
call timing πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
call timing2 πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
call cc_timing πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
call cc_timing2 πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
di timing GS πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
div timing πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
ei sequence πŸ‘ πŸ‘ πŸ‘ πŸ‘ ❌ πŸ‘ πŸ‘
ei timing πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
halt ime0 ei πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
halt ime0 nointr_timing πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ ❌ πŸ‘
halt ime1 timing πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
halt ime1 timing2 GS πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ ❌ πŸ‘
if ie registers πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ ❌ πŸ‘
intr timing πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ ❌ πŸ‘
jp timing πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
jp cc timing πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
ld hl sp e timing πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
oam dma_restart πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘ ❌
oam dma start πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
oam dma timing πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘ ❌
pop timing πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
push timing πŸ‘ ❌ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘
rapid di ei πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
ret timing πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
ret cc timing πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
reti timing πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
reti intr timing πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
rst timing πŸ‘ ❌ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘

Instructions

Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours
daa πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘

Interrupt handling

Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours
ie push πŸ‘ ❌ ❌ ❌ ❌ πŸ‘ πŸ‘

OAM DMA

Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours
basic πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
reg_read πŸ‘ πŸ‘ πŸ‘ ❌ ❌ πŸ‘ πŸ‘
sources dmgABCmgbS πŸ‘ πŸ‘ ❌ ❌ ❌ ❌ πŸ‘

Serial

Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours
boot sclk align dmgABCmgb ❌ πŸ‘ πŸ‘ ❌ ❌ πŸ‘ πŸ‘

PPU

Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours
hblank ly scx timing GS πŸ‘ πŸ‘ ❌ ❌ πŸ‘ ❌ ❌
intr 1 2 timing GS πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ ❌ ❌
intr 2 0 timing πŸ‘ πŸ‘ ❌ πŸ‘ πŸ‘ ❌ ❌
intr 2 mode0 timing πŸ‘ πŸ‘ ❌ ❌ πŸ‘ ❌ πŸ‘
intr 2 mode3 timing πŸ‘ πŸ‘ ❌ ❌ πŸ‘ ❌ πŸ‘
intr 2 oam ok timing πŸ‘ πŸ‘ ❌ ❌ πŸ‘ ❌ πŸ‘
intr 2 mode0 timing sprites ❌ πŸ‘ ❌ ❌ πŸ‘ ❌ ❌
lcdon timing dmgABCmgbS ❌ πŸ‘ ❌ ❌ ❌ ❌ ❌
lcdon write timing GS ❌ πŸ‘ ❌ ❌ ❌ ❌ ❌
stat irq blocking ❌ πŸ‘ πŸ‘ ❌ πŸ‘ ❌ πŸ‘
stat lyc onoff ❌ πŸ‘ ❌ ❌ ❌ ❌ ❌
vblank stat intr GS πŸ‘ πŸ‘ ❌ πŸ‘ πŸ‘ ❌ πŸ‘

Timer

Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours
div write πŸ‘ πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘
rapid toggle πŸ‘ πŸ‘ ❌ ❌ πŸ‘ πŸ‘ πŸ‘
tim00 div trigger πŸ‘ πŸ‘ πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘
tim00 πŸ‘ πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘
tim01 div trigger πŸ‘ πŸ‘ ❌ ❌ πŸ‘ πŸ‘ πŸ‘
tim01 πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘ πŸ‘
tim10 div trigger πŸ‘ πŸ‘ ❌ ❌ πŸ‘ πŸ‘ πŸ‘
tim10 πŸ‘ πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘
tim11 div trigger πŸ‘ πŸ‘ ❌ ❌ πŸ‘ πŸ‘ πŸ‘
tim11 πŸ‘ πŸ‘ ❌ πŸ‘ πŸ‘ πŸ‘ πŸ‘
tima reload πŸ‘ πŸ‘ ❌ ❌ πŸ‘ πŸ‘ πŸ‘
tima write reloading πŸ‘ πŸ‘ ❌ ❌ πŸ‘ πŸ‘ πŸ‘
tma write reloading πŸ‘ πŸ‘ ❌ ❌ πŸ‘ πŸ‘ πŸ‘

MBC

Test mooneye-gb BGB Gambatte Higan MESS VerilogBoy Ours
MBC1 N/A πŸ‘ N/A N/A N/A N/A πŸ‘
MBC5 N/A πŸ‘ N/A N/A N/A N/A πŸ‘

Note: MBC3 test ROM was not created at the time of testing.

About

A systemVerilog implementation of Game Boy on DE1-SoC

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published