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  • Stanford University
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Popular repositories

  1. USB-Host USB-Host Public

    Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the bus.

    SystemVerilog 11 2

  2. Team-SDK-545 Team-SDK-545 Public

    An FPGA design project by Kais Kudrolli, Sohil Shah, and DongJoon Park for 18-545 at Carnegie Mellon University.

    VHDL 9 1

  3. Calculus-Calculator Calculus-Calculator Public

    A python implementation of a calculator that can graph integrals and derivatives as well as take the symbolic derivative of a function in terms of x.

    Python 8

  4. cs205l_final cs205l_final Public

    Final project for CS205L at Stanford University.

    Python 1

  5. munbattlesim munbattlesim Public

    Model UN battle simulator project: A way to simulate battles, troop movement, and resource movement in a MUN Joint Crisis Committee

    Python

  6. Testbench Testbench Public

    A System Verilog testbench used to find faults in a black box calculator design.

    SystemVerilog