Initial implementation of gfx942 #6358
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Change-Id: Id31ca3ba5356d021cade2abc3e3f51f9f3b4d211
Change-Id: I1454bb0b91518bfcf7a04506e40b98387cdf8ed9
Change-Id: Id9c03fe451d1d28a3c23a77f161a2600f016c7e4
dalg24
reviewed
Aug 14, 2023
Co-authored-by: Daniel Arndt <arndtd@ornl.gov>
Co-authored-by: Damien L-G <dalg24+github@gmail.com>
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Can you say a word about the thread fences that are being added? |
Technically, this was a violation of the memory model, because there was no guarantee that the write for the intermediate reduction values became visible before the read by the last block to do the second stage. This never bit us because it was quite unlikely on the hardware we're running on, but... shall we say that may not always hold. I've tested correctness and performance of several LAMMPS benchmarks, a regular dot product, and the yAx tutorial example on MI-250, and saw essentially no impact from unconditionally including it. |
Rombur
reviewed
Aug 15, 2023
Change-Id: Ibd028fddeedf8e0fdda50b72625ab62cee6fa71e
Rombur
approved these changes
Aug 15, 2023
masterleinad
approved these changes
Aug 15, 2023
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CUDA failure unrelated |
Closed
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