Fixes for HW debugging (Michael Walle)

boards/milkymist-one/rtl/system.v

@@ -255,6 +255,9 @@ wire [2:0]	cpuibus_cti,
 		ethernettxbus_cti;
 
 wire [31:0]	cpuibus_dat_r,
+`ifdef CFG_HW_DEBUG_ENABLED
+		cpuibus_dat_w,
+`endif
 		cpudbus_dat_r,
 		cpudbus_dat_w,
 		ac97bus_dat_r,
@@ -265,8 +268,14 @@ wire [31:0]	cpuibus_dat_r,
 		ethernettxbus_dat_r;
 
 wire [3:0]	cpudbus_sel;
+`ifdef CFG_HW_DEBUG_ENABLED
+wire [3:0]	cpuibus_sel;
+`endif
 
 wire		cpudbus_we,
+`ifdef CFG_HW_DEBUG_ENABLED
+		cpuibus_we,
+`endif
 		ac97bus_we;
 
 wire		cpuibus_cyc,
@@ -349,12 +358,21 @@ xbar xbar(
 	.sys_rst(sys_rst),
 
 	// Master 0
+`ifdef CFG_HW_DEBUG_ENABLED
+	.m0_dat_i(cpuibus_dat_w),
+`else
 	.m0_dat_i(32'hx),
+`endif
 	.m0_dat_o(cpuibus_dat_r),
 	.m0_adr_i(cpuibus_adr),
 	.m0_cti_i(cpuibus_cti),
+`ifdef CFG_HW_DEBUG_ENABLED
+	.m0_we_i(cpuibus_we),
+	.m0_sel_i(cpuibus_sel),
+`else
 	.m0_we_i(1'b0),
 	.m0_sel_i(4'hf),
+`endif
 	.m0_cyc_i(cpuibus_cyc),
 	.m0_stb_i(cpuibus_stb),
 	.m0_ack_o(cpuibus_ack),
@@ -750,12 +768,21 @@ lm32_top cpu(
 
 	.I_ADR_O(cpuibus_adr),
 	.I_DAT_I(cpuibus_dat_r),
+`ifdef CFG_HW_DEBUG_ENABLED
+	.I_DAT_O(cpuibus_dat_w),
+	.I_SEL_O(cpuibus_sel),
+`else
 	.I_DAT_O(),
 	.I_SEL_O(),
+`endif
 	.I_CYC_O(cpuibus_cyc),
 	.I_STB_O(cpuibus_stb),
 	.I_ACK_I(cpuibus_ack),
+`ifdef CFG_HW_DEBUG_ENABLED
+	.I_WE_O(cpuibus_we),
+`else
 	.I_WE_O(),
+`endif
 	.I_CTI_O(cpuibus_cti),
 	.I_LOCK_O(),
 	.I_BTE_O(),

cores/norflash16/rtl/norflash16.v

@@ -1,6 +1,7 @@
 /*
  * Milkymist VJ SoC
  * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
+ * Copyright (C) 2010 Michael Walle
  *
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -31,7 +32,7 @@ module norflash16 #(
 	input wb_cyc_i,
 	output reg wb_ack_o,
 	input wb_we_i,
-	
+
 	output [adr_width-1:0] flash_adr,
 	inout [15:0] flash_d,
 	output reg flash_oe_n,
@@ -42,12 +43,12 @@ reg [adr_width-1:0] flash_adr_r;
 reg [15:0] flash_do;
 reg lsb;
 
-assign flash_adr = {flash_adr_r[adr_width-1:1], flash_adr_r[0] ^ lsb};
+assign two_cycle_transfer = (wb_sel_i == 4'b1111);
+assign flash_adr = {flash_adr_r[adr_width-1:1], (two_cycle_transfer) ? lsb : flash_adr_r[0]};
 assign flash_d = flash_oe_n ? flash_do : 16'bz;
 
 reg load;
 reg store;
-assign two_cycle_transfer = (wb_sel_i == 4'b1111);
 
 always @(posedge sys_clk) begin
 	flash_oe_n <= 1'b1;
@@ -64,19 +65,20 @@ always @(posedge sys_clk) begin
 				default: flash_do <= 16'hxxxx;
 			endcase
 		else
-			flash_oe_n <= 0;
+			flash_oe_n <= 1'b0;
 	end
+
 	if(load) begin
 		casex({wb_sel_i, lsb})
-			5'b0001x: wb_dat_o[7:0]   <= flash_d[7:0];
-			5'b0010x: wb_dat_o[15:8]  <= flash_d[15:8];
-			5'b0100x: wb_dat_o[23:16] <= flash_d[7:0];
-			5'b1000x: wb_dat_o[31:24] <= flash_d[15:8];
-			5'b0011x: wb_dat_o[15:0]  <= flash_d;
-			5'b1100x: wb_dat_o[31:16] <= flash_d;
+			5'b0001x: wb_dat_o <= {4{flash_d[7:0]}};
+			5'b0010x: wb_dat_o <= {4{flash_d[15:8]}};
+			5'b0100x: wb_dat_o <= {4{flash_d[7:0]}};
+			5'b1000x: wb_dat_o <= {4{flash_d[15:8]}};
+			5'b0011x: wb_dat_o <= {2{flash_d}};
+			5'b1100x: wb_dat_o <= {2{flash_d}};
 			5'b11110: begin wb_dat_o[31:16] <= flash_d; lsb <= ~lsb; end
 			5'b11111: begin wb_dat_o[15:0]  <= flash_d; lsb <= ~lsb; end
-			default:  wb_dat_o[31:0] <= 32'hxxxxxxxx;
+			default:  wb_dat_o <= 32'hxxxxxxxx;
 		endcase
 	end
 	if(store)
@@ -107,20 +109,21 @@ always @(posedge sys_clk) begin
 	end
 end
 
+parameter IDLE		= 2'd0;
+parameter DELAYRD	= 2'd1;
+parameter DELAYWR	= 2'd2;
+parameter ACK		= 2'd3;
+
 reg [1:0] state;
 reg [1:0] next_state;
+
 always @(posedge sys_clk) begin
 	if(sys_rst)
-		state <= 1'b0;
+		state <= IDLE;
 	else
 		state <= next_state;
 end
 
-parameter IDLE		= 2'd0;
-parameter DELAYRD	= 2'd1;
-parameter DELAYWR	= 2'd2;
-parameter ACK		= 2'd3;
-
 always @(*) begin
 	next_state = state;
 	counter_en = 1'b0;
@@ -158,7 +161,7 @@ always @(*) begin
 
 		ACK: begin
 			wb_ack_o = 1'b1;
-			next_state = 2'd0;
+			next_state = IDLE;
 		end
 	endcase
 end

cores/norflash16/test/tb_norflash16.v

@@ -27,14 +27,13 @@ wire [31:0] wb_dat_o;
 reg wb_cyc_i;
 reg wb_stb_i;
 wire wb_ack_o;
-
-wire [6:0] aceusb_a;
-wire [15:0] aceusb_d;
+reg [3:0] wb_sel_i;
 
 wire [21:0] flash_adr;
-reg [15:0] flash_d;
+inout [15:0] flash_d;
+reg [15:0] flash_do;
 
-always @(flash_adr) #110 flash_d <= flash_adr[15:0] + 8'd1;
+always @(flash_adr) #110 flash_do <= flash_adr[15:0] + 16'b1;
 
 norflash16 dut(
 	.sys_clk(sys_clk),
@@ -45,11 +44,16 @@ norflash16 dut(
 	.wb_cyc_i(wb_cyc_i),
 	.wb_stb_i(wb_stb_i),
 	.wb_ack_o(wb_ack_o),
+	.wb_sel_i(wb_sel_i),
 
 	.flash_adr(flash_adr),
-	.flash_d(flash_d)
+	.flash_d(flash_d),
+	.flash_oe_n(flash_oe_n),
+	.flash_we_n(flash_we_n)
 );
 
+assign flash_d = flash_oe_n ? 16'bz : flash_do;
+
 task wbread;
 	input [31:0] address;
 	integer i;
@@ -77,12 +81,16 @@ task wbread;
 endtask
 
 initial begin
+	$dumpfile("norflash16.vcd");
+	$dumpvars(-1, dut);
+
 	sys_rst = 1'b1;
 	sys_clk = 1'b0;
 
 	wb_adr_i = 32'h00000000;
 	wb_cyc_i = 1'b0;
 	wb_stb_i = 1'b0;
+	wb_sel_i = 4'b1111;
 
 	#5 sys_clk = 1'b1;
 	#5 sys_clk = 1'b0;
@@ -91,7 +99,25 @@ initial begin
 	#5 sys_clk = 1'b1;
 	#5 sys_clk = 1'b0;
 
-	wbread(32'h00000020);
+	wb_sel_i = 4'b1111;
+	wbread(32'h0000fff0);
+
+	wb_sel_i = 4'b0001;
+	wbread(32'h0000fff0);
+
+	wb_sel_i = 4'b0010;
+	wbread(32'h0000fff1);
+
+	wb_sel_i = 4'b0100;
+	wbread(32'h0000fff2);
+
+	wb_sel_i = 4'b1000;
+	wbread(32'h0000fff3);
+
+	wb_sel_i = 4'b0100;
+	wbread(32'h0000fff0);
+
+	wb_sel_i = 4'b1111;
 	wbread(32'h00000010);
 	#5 sys_clk = 1'b1;
 	#5 sys_clk = 1'b0;