Changes for processors grid numa style

[wmbrownIntel]

As core counts per socket and data movement bottlenecks increase, it can be better to optimize the numa mapping within a node. This adds a processors option to specify the number of numa domains for the processors grid numa style, with the default being 2. It also simplifies the numa mapping algorithm with more aggressive optimization to reduce comm between numa domains.

Summary

Related Issue(s)

Author(s)

Mike Brown, Intel

Licensing

By submitting this pull request, I agree, that my contribution will be included in LAMMPS and redistributed under either the GNU General Public License version 2 (GPL v2) or the GNU Lesser General Public License version 2.1 (LGPL v2.1).

Backward Compatibility

I chose the numa domains option to be a separate keyword for processors, preserving backward compatibility. Of course, the other option, that might be more natural to the LAMMPS command style but break compatibility, would be to make this an argument for 'numa'.

Implementation Notes

Post Submission Checklist

• The feature or features in this pull request is complete
• Licensing information is complete
• Corresponding author information is complete
• The source code follows the LAMMPS formatting guidelines
• Suitable new documentation files and/or updates to the existing docs are included
• The added/updated documentation is integrated and tested with the documentation build system
• The feature has been verified to work with the conventional build system
• The feature has been verified to work with the CMake based build system
• Suitable tests have been added to the unittest tree.
• A package specific README file has been included or updated
• One or more example input decks are included

Further Information, Files, and Links

[stanmoore1]

Looks good, I approve. Thanks @wmbrownIntel

[sjplimp]

thanks Mike