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Use a different default location for mediating ancilla states in CNOTs when the layout does not supply one #115

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@gwwatkin gwwatkin commented Mar 1, 2024

Closes #111

@gwwatkin gwwatkin marked this pull request as draft March 1, 2024 08:50
@gwwatkin gwwatkin force-pushed the fix-ancilla-locatition-for-cnots-with-no-dedicated-cell branch from acc60f8 to 0fed078 Compare April 28, 2024 19:38
@gwwatkin gwwatkin changed the title [WIP] Use a different default location for mediating ancilla states in CNOTs when the layout does not supply one Use a different default location for mediating ancilla states in CNOTs when the layout does not supply one Apr 28, 2024
@gwwatkin gwwatkin marked this pull request as ready for review April 28, 2024 19:52
@tylerrleblond
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This does not work as expected for EDPC layouts. The compilation hangs, for example, for the following test:

INPUT="
OPENQASM 2.0;
include "qelib1.inc";

qreg q[25];
cx q[0],q[1];
cx q[2],q[3];
cx q[4],q[5];
cx q[6],q[7];
"
echo "$INPUT" | lsqecc_slicer -q -L edpc

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CNOT gates hang for layouts with no 'A' specified
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