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Refactoring py/ports (#131)
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* - refactor creation of ImplicitVarPort into a common function

* - refactor creation of ImplicitVarPort into a common function

* - refactor inheritage of PyInPort and PyOutPort to a common parent class and removed anonymous argument list for their init functions

* - Adressed requested changes of PR (rename of class, adding comments)

* - fix unit tests
- try resolving conflict

* - Adressed requested changes of PR (adding comments)
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PhilippPlank committed Feb 16, 2022
1 parent 29fd444 commit e253a6a
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Showing 6 changed files with 535 additions and 109 deletions.
4 changes: 2 additions & 2 deletions src/lava/magma/compiler/builders/builder.py
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@
from lava.magma.compiler.utils import VarInitializer, PortInitializer, \
VarPortInitializer
from lava.magma.core.model.py.ports import (
AbstractPyPort,
AbstractPyIOPort,
PyInPort,
PyOutPort,
PyRefPort,
Expand Down Expand Up @@ -340,7 +340,7 @@ def build(self):
for name, p in self.py_ports.items():
# Build PyPort
lt = self._get_lava_type(name)
port_cls = ty.cast(ty.Type[AbstractPyPort], lt.cls)
port_cls = ty.cast(ty.Type[AbstractPyIOPort], lt.cls)
csp_ports = []
if name in self.csp_ports:
csp_ports = self.csp_ports[name]
Expand Down
17 changes: 3 additions & 14 deletions src/lava/magma/compiler/compiler.py
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@
from lava.magma.core.model.py.ports import RefVarTypeMapping
from lava.magma.core.model.sub.model import AbstractSubProcessModel
from lava.magma.core.process.ports.ports import AbstractPort, VarPort, \
ImplicitVarPort
ImplicitVarPort, RefPort
from lava.magma.core.process.process import AbstractProcess
from lava.magma.core.resources import CPU, NeuroCore
from lava.magma.core.run_configs import RunConfig
Expand Down Expand Up @@ -217,21 +217,10 @@ def _propagate_var_ports(proc: AbstractProcess):
for vp in proc.var_ports:
v = vp.var.aliased_var
if v is not None:
sub_proc = v.process
# Create an implicit Var port in the sub process
new_vp = ImplicitVarPort(v)
# Propagate name and parent process of Var to VarPort
new_vp.name = "_" + v.name + "_implicit_port"
new_vp.process = sub_proc
# VarPort name could shadow existing attribute
if hasattr(sub_proc, new_vp.name):
raise AssertionError(
"Name of implicit VarPort might conflict"
" with existing attribute.")
setattr(sub_proc, new_vp.name, new_vp)
sub_proc.var_ports.add_members({new_vp.name: new_vp})
imp_vp = RefPort.create_implicit_var_port(v)
# Connect the VarPort to the new VarPort
vp.connect(new_vp)
vp.connect(imp_vp)

def _expand_sub_proc_model(self,
model_cls: ty.Type[AbstractSubProcessModel],
Expand Down

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