Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Virtual ports between RefPorts and VarPorts #195

Merged
merged 29 commits into from Mar 2, 2022

Conversation

mathisrichter
Copy link
Contributor

Issue Number: #194

Objective of pull request: Provide support for virtual ports between RefPorts and VarPorts

Pull request checklist

Your PR fulfills the following requirements:

  • Issue created that explains the change and why it's needed
  • Tests are part of the PR (for bug fixes / features)
  • Docs reviewed and added / updated if needed (for bug fixes / features)
  • PR conforms to Coding Conventions
  • PR applys BSD 3-clause or LGPL2.1+ Licenses to all code files
  • Lint (pyb) passes locally
  • Build tests (pyb -E unit) or (python -m unittest) passes locally

Pull request type

Please check your PR type:

  • Bugfix
  • Feature
  • Code style update (formatting, renaming)
  • Refactoring (no functional changes, no api changes)
  • Build related changes
  • Documentation changes
  • Other (please describe):

What is the current behavior?

  • Virtual ports between RefPorts and VarPorts raise an exception

What is the new behavior?

  • Virtual ports (reshape/flatten/transpose) between RefPorts and VarPorts work.

Does this introduce a breaking change?

  • Yes
  • No

Supplemental information

bamsumit and others added 25 commits January 20, 2022 16:26
Signed-off-by: bamsumit <bam_sumit@hotmail.com>
Signed-off-by: Mathis Richter <mathis.richter@intel.com>
Signed-off-by: Mathis Richter <mathis.richter@intel.com>
Signed-off-by: Mathis Richter <mathis.richter@intel.com>
Signed-off-by: Mathis Richter <mathis.richter@intel.com>
Signed-off-by: Mathis Richter <mathis.richter@intel.com>
Signed-off-by: Mathis Richter <mathis.richter@intel.com>
…t (wip)

Signed-off-by: Mathis Richter <mathis.richter@intel.com>
� Conflicts:
�	src/lava/magma/compiler/compiler.py
�	src/lava/magma/core/model/py/ports.py
�	tests/lava/magma/core/model/py/test_ports.py
Signed-off-by: Mathis Richter <mathis.richter@intel.com>
…hierarchical Processes

Signed-off-by: Mathis Richter <mathis.richter@intel.com>
Signed-off-by: Mathis Richter <mathis.richter@intel.com>
Signed-off-by: Mathis Richter <mathis.richter@intel.com>
Signed-off-by: Mathis Richter <mathis.richter@intel.com>
� Conflicts:
�	src/lava/magma/compiler/compiler.py
Signed-off-by: Mathis Richter <mathis.richter@intel.com>
…ical Processes.

Signed-off-by: Mathis Richter <mathis.richter@intel.com>
Signed-off-by: Mathis Richter <mathis.richter@intel.com>
Signed-off-by: Mathis Richter <mathis.richter@intel.com>
Signed-off-by: Mathis Richter <mathis.richter@intel.com>
…hical Processes.

Signed-off-by: Mathis Richter <mathis.richter@intel.com>
Signed-off-by: Mathis Richter <mathis.richter@intel.com>
Copy link
Contributor

@PhilippPlank PhilippPlank left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Nice!

src/lava/magma/core/process/ports/ports.py Show resolved Hide resolved
Signed-off-by: Mathis Richter <mathis.richter@intel.com>
@mathisrichter mathisrichter merged commit 1e1474b into lava-nc:main Mar 2, 2022
@mathisrichter mathisrichter deleted the permute branch March 2, 2022 14:33
mgkwill pushed a commit that referenced this pull request Jul 6, 2022
* changed Node to Nodes
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

None yet

5 participants