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ipq806x: fix wireless regression on k4.9, sync with QSDK #1559

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ipq806x: fix wireless regression on k4.9, sync with QSDK #1559

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8d7faff
ipq806x: fix wireless regression
dissent1 Dec 1, 2017
f7f071c
ipq806x: force 2nd pci slot into gen1 mode
dissent1 Jul 6, 2017
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3 changes: 1 addition & 2 deletions target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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Expand Up @@ -161,12 +161,11 @@

pcie0: pci@1b500000 {
status = "ok";
phy-tx0-term-offset = <7>;
};

pcie1: pci@1b700000 {
status = "ok";
phy-tx0-term-offset = <7>;
force_gen1 = <1>;
};

nand@1ac00000 {
Expand Down
3 changes: 1 addition & 2 deletions target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-c2600.dts
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Expand Up @@ -346,12 +346,11 @@

pcie0: pci@1b500000 {
status = "ok";
phy-tx0-term-offset = <7>;
};

pcie1: pci@1b700000 {
status = "ok";
phy-tx0-term-offset = <7>;
force_gen1 = <1>;
};

mdio0: mdio {
Expand Down
1 change: 1 addition & 0 deletions target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
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Expand Up @@ -193,6 +193,7 @@
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
force_gen1 = <1>;
};

nand@1ac00000 {
Expand Down
10 changes: 2 additions & 8 deletions target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
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Expand Up @@ -157,19 +157,13 @@

pcie0: pci@1b500000 {
status = "ok";
phy-tx0-term-offset = <7>;
};

pcie1: pci@1b700000 {
status = "ok";
phy-tx0-term-offset = <7>;
force_gen1 = <1>;
};

pcie2: pci@1b900000 {
status = "ok";
phy-tx0-term-offset = <7>;
};


nand@1ac00000 {
status = "ok";

Expand Down
1 change: 1 addition & 0 deletions target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
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Expand Up @@ -168,6 +168,7 @@

pcie1: pci@1b700000 {
status = "ok";
force_gen1 = <1>;
};

nand@1ac00000 {
Expand Down
1 change: 1 addition & 0 deletions target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
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Expand Up @@ -198,6 +198,7 @@
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
force_gen1 = <1>;
};

nand@1ac00000 {
Expand Down
3 changes: 1 addition & 2 deletions target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
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Expand Up @@ -259,12 +259,11 @@

pcie0: pci@1b500000 {
status = "ok";
phy-tx0-term-offset = <7>;
};

pcie1: pci@1b700000 {
status = "ok";
phy-tx0-term-offset = <7>;
force_gen1 = <1>;
};

mdio0: mdio {
Expand Down
6 changes: 6 additions & 0 deletions target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064.dtsi
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Expand Up @@ -1051,6 +1051,8 @@

perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;

phy-tx0-term-offset = <7>;

status = "disabled";
};

Expand Down Expand Up @@ -1103,6 +1105,8 @@

perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;

phy-tx0-term-offset = <7>;

status = "disabled";
};

Expand Down Expand Up @@ -1155,6 +1159,8 @@

perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;

phy-tx0-term-offset = <7>;

status = "disabled";
};

Expand Down
1 change: 1 addition & 0 deletions target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
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Expand Up @@ -229,6 +229,7 @@
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
force_gen1 = <1>;
};

mdio0: mdio {
Expand Down
3 changes: 1 addition & 2 deletions target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-r7800.dts
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Expand Up @@ -299,12 +299,11 @@

pcie0: pci@1b500000 {
status = "ok";
phy-tx0-term-offset = <7>;
};

pcie1: pci@1b700000 {
status = "ok";
phy-tx0-term-offset = <7>;
force_gen1 = <1>;
};

nand@1ac00000 {
Expand Down
95 changes: 95 additions & 0 deletions target/linux/ipq806x/patches-4.9/0071-1-PCI-qcom-Fixed-IPQ806x-specific-clocks.patch
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@@ -0,0 +1,95 @@
From 86655aa14304ca88a8ce8847276147dbc1a83238 Mon Sep 17 00:00:00 2001
From: Sham Muthayyan <smuthayy@codeaurora.org>
Date: Tue, 19 Jul 2016 18:44:49 +0530
Subject: PCI: qcom: Fixed IPQ806x specific clocks

Change-Id: I488e1bc707d6a22b37a338f41935e3922009ba5e
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
---
drivers/pci/host/pcie-qcom.c | 38 +++++++++++++++++++++++++++++++++-----
1 file changed, 33 insertions(+), 5 deletions(-)

--- a/drivers/pci/host/pcie-qcom.c
+++ b/drivers/pci/host/pcie-qcom.c
@@ -53,6 +53,8 @@ struct qcom_pcie_resources_v0 {
struct clk *iface_clk;
struct clk *core_clk;
struct clk *phy_clk;
+ struct clk *aux_clk;
+ struct clk *ref_clk;
struct reset_control *pci_reset;
struct reset_control *axi_reset;
struct reset_control *ahb_reset;
@@ -160,6 +162,14 @@ static int qcom_pcie_get_resources_v0(st
if (IS_ERR(res->phy_clk))
return PTR_ERR(res->phy_clk);

+ res->aux_clk = devm_clk_get(dev, "aux");
+ if (IS_ERR(res->aux_clk))
+ return PTR_ERR(res->aux_clk);
+
+ res->ref_clk = devm_clk_get(dev, "ref");
+ if (IS_ERR(res->ref_clk))
+ return PTR_ERR(res->ref_clk);
+
res->pci_reset = devm_reset_control_get(dev, "pci");
if (IS_ERR(res->pci_reset))
return PTR_ERR(res->pci_reset);
@@ -227,6 +237,8 @@ static void qcom_pcie_deinit_v0(struct q
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
clk_disable_unprepare(res->phy_clk);
+ clk_disable_unprepare(res->aux_clk);
+ clk_disable_unprepare(res->ref_clk);
regulator_disable(res->vdda);
regulator_disable(res->vdda_phy);
regulator_disable(res->vdda_refclk);
@@ -269,16 +281,28 @@ static int qcom_pcie_init_v0(struct qcom
goto err_assert_ahb;
}

+ ret = clk_prepare_enable(res->core_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable core clock\n");
+ goto err_clk_core;
+ }
+
ret = clk_prepare_enable(res->phy_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable phy clock\n");
goto err_clk_phy;
}

- ret = clk_prepare_enable(res->core_clk);
+ ret = clk_prepare_enable(res->aux_clk);
if (ret) {
- dev_err(dev, "cannot prepare/enable core clock\n");
- goto err_clk_core;
+ dev_err(dev, "cannot prepare/enable aux clock\n");
+ goto err_clk_aux;
+ }
+
+ ret = clk_prepare_enable(res->ref_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable ref clock\n");
+ goto err_clk_ref;
}

ret = reset_control_deassert(res->ahb_reset);
@@ -327,10 +351,14 @@ static int qcom_pcie_init_v0(struct qcom
return 0;

err_deassert_ahb:
- clk_disable_unprepare(res->core_clk);
-err_clk_core:
+ clk_disable_unprepare(res->ref_clk);
+err_clk_ref:
+ clk_disable_unprepare(res->aux_clk);
+err_clk_aux:
clk_disable_unprepare(res->phy_clk);
err_clk_phy:
+ clk_disable_unprepare(res->core_clk);
+err_clk_core:
clk_disable_unprepare(res->iface_clk);
err_assert_ahb:
regulator_disable(res->vdda_phy);
85 changes: 85 additions & 0 deletions target/linux/ipq806x/patches-4.9/0071-2-PCI-qcom-Fixed-IPQ806x-PCIE-reset-changes.patch
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@@ -0,0 +1,85 @@
From 490d103232287eb51c92c49a4ef8865fd0a9d59e Mon Sep 17 00:00:00 2001
From: Sham Muthayyan <smuthayy@codeaurora.org>
Date: Tue, 19 Jul 2016 18:58:18 +0530
Subject: PCI: qcom: Fixed IPQ806x PCIE reset changes

Change-Id: Ia6590e960b9754b1e8b7a51f318788cd63e9e321
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
---
drivers/pci/host/pcie-qcom.c | 24 +++++++++++++++++++-----
1 file changed, 19 insertions(+), 5 deletions(-)

--- a/drivers/pci/host/pcie-qcom.c
+++ b/drivers/pci/host/pcie-qcom.c
@@ -60,6 +60,7 @@ struct qcom_pcie_resources_v0 {
struct reset_control *ahb_reset;
struct reset_control *por_reset;
struct reset_control *phy_reset;
+ struct reset_control *ext_reset;
struct regulator *vdda;
struct regulator *vdda_phy;
struct regulator *vdda_refclk;
@@ -190,6 +191,10 @@ static int qcom_pcie_get_resources_v0(st
if (IS_ERR(res->phy_reset))
return PTR_ERR(res->phy_reset);

+ res->ext_reset = devm_reset_control_get(dev, "ext");
+ if (IS_ERR(res->ext_reset))
+ return PTR_ERR(res->ext_reset);
+
return 0;
}

@@ -234,6 +239,7 @@ static void qcom_pcie_deinit_v0(struct q
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
reset_control_assert(res->pci_reset);
+ reset_control_assert(res->ext_reset);
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
clk_disable_unprepare(res->phy_clk);
@@ -251,6 +257,12 @@ static int qcom_pcie_init_v0(struct qcom
u32 val;
int ret;

+ ret = reset_control_assert(res->ahb_reset);
+ if (ret) {
+ dev_err(dev, "cannot assert ahb reset\n");
+ return ret;
+ }
+
ret = regulator_enable(res->vdda);
if (ret) {
dev_err(dev, "cannot enable vdda regulator\n");
@@ -269,16 +281,16 @@ static int qcom_pcie_init_v0(struct qcom
goto err_vdda_phy;
}

- ret = reset_control_assert(res->ahb_reset);
+ ret = reset_control_deassert(res->ext_reset);
if (ret) {
- dev_err(dev, "cannot assert ahb reset\n");
- goto err_assert_ahb;
+ dev_err(dev, "cannot assert ext reset\n");
+ goto err_reset_ext;
}

ret = clk_prepare_enable(res->iface_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable iface clock\n");
- goto err_assert_ahb;
+ goto err_iface;
}

ret = clk_prepare_enable(res->core_clk);
@@ -360,7 +372,9 @@ err_clk_phy:
clk_disable_unprepare(res->core_clk);
err_clk_core:
clk_disable_unprepare(res->iface_clk);
-err_assert_ahb:
+err_iface:
+ reset_control_assert(res->ext_reset);
+err_reset_ext:
regulator_disable(res->vdda_phy);
err_vdda_phy:
regulator_disable(res->vdda_refclk);