Fix style error

leonardt · May 6, 2019 · 2a5d2a7 · 2a5d2a7
1 parent 5815498
commit 2a5d2a7
Showing 1 changed file with 0 additions and 1 deletion.
diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py
@@ -86,7 +86,6 @@ def make_name(self, port):
             name = verilog_name(port.name)
         return name
 
-
     def make_poke(self, i, action):
         name = self.make_name(action.port)
         # For now we assume that verilog can handle big ints