Fix string syntax

leonardt · Jun 5, 2019 · 30fd2c0 · 30fd2c0
1 parent 70ab161
commit 30fd2c0
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py
@@ -23,7 +23,7 @@ def generate_nonce(length=8):
 module {circuit_name}_tb;
 // Adding a random nonce string to try to force ncsim to recompile, see
 // https://github.com/StanfordAHA/lassen/issues/111 for the issue
-string nonce = {nonce}
+string nonce = "{nonce}";
 
 {declarations}