Merge pull request #107 from leonardt/patch-sv-literals

Explicitly set integer literal size in SV backend

fault/system_verilog_target.py

@@ -85,11 +85,12 @@ def make_name(self, port):
         return name
 
     def process_value(self, port, value):
-        if isinstance(port, m.SIntType) and value < 0:
-            # Handle sign extension for verilator since it expects and
-            # unsigned c type
+        if isinstance(value, BitVector):
+            value = f"{len(value)}'d{value.as_uint()}"
+        elif isinstance(port, m.SIntType) and value < 0:
             port_len = len(port)
             value = BitVector(value, port_len).as_uint()
+            value = f"{port_len}'d{value}"
         elif value is fault.UnknownValue:
             value = "'X"
         elif isinstance(value, actions.Peek):