Fixup logic

leonardt · Jun 5, 2019 · 494c060 · 494c060
1 parent 7d2a560
commit 494c060
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py
@@ -286,8 +286,8 @@ def run(self, actions, power_args={}):
         if check_timestamp:
             new_stat_result = os.stat(tb_file)
             new_times = (new_stat_result.st_atime, new_stat_result.st_mtime)
-            if new_times[1] <= old_times[1]:
-                new_times = (new_times[0], old_times[1] + 1)
+            if old_times[0] <= new_times[0] or new_times[1] <= old_times[1]:
+                new_times = (old_times[0] + 1, old_times[1] + 1)
                 os.utime(tb_file, times=new_times)
         verilog_libraries = " ".join(str(x) for x in
                                      self.include_verilog_libraries)