Merge 95592eb into 104502c

fault/verilator_target.py

@@ -37,11 +37,12 @@
 
 class VerilatorTarget(Target):
     def __init__(self, circuit, actions, directory="build/",
-                 flags=[], skip_compile=False):
+                 flags=[], skip_compile=False, include_verilog_files=[]):
         super().__init__(circuit, actions)
         self.directory = Path(directory)
         self.flags = flags
         self.skip_compile = skip_compile
+        self.include_verilog_files = include_verilog_files
 
     @staticmethod
     def generate_action_code(i, action):
@@ -110,7 +111,8 @@ def run(self):
         # the Makefile output by verilator, and finally run the executable
         # created by verilator.
         verilator_cmd = verilator_utils.verilator_cmd(
-            top, verilog_file.name, driver_file.name, self.flags)
+            top, verilog_file.name, self.include_verilog_files,
+            driver_file.name, self.flags)
         assert not self.run_from_directory(verilator_cmd)
         verilator_make_cmd = verilator_utils.verilator_make_cmd(top)
         assert not self.run_from_directory(verilator_make_cmd)

fault/verilator_utils.py

@@ -2,7 +2,8 @@
 import fault.actions as actions
 
 
-def verilator_cmd(top, verilog_filename, driver_filename, verilator_flags):
+def verilator_cmd(top, verilog_filename, include_verilog_files, driver_filename,
+                  verilator_flags):
     DEFAULT_FLAGS = [
         "-Wall",
         "-Wno-INCABSPATH",
@@ -11,8 +12,10 @@ def verilator_cmd(top, verilog_filename, driver_filename, verilator_flags):
     flags = DEFAULT_FLAGS
     flags.extend(verilator_flags)
     flag_str = " ".join(flags)
+    include_str = ' '.join(f'-v {file_}' for file_ in include_verilog_files)
     return (f"verilator {flag_str} "
             f"--cc {verilog_filename} "
+            f"{include_str} "
             f"--exe {driver_filename} "
             f"--top-module {top}")
 

tests/build/.gitignore

@@ -0,0 +1,2 @@
+*
+!.gitignore

tests/sb_dff_sim.v

@@ -0,0 +1,7 @@
+// From https://raw.githubusercontent.com/YosysHQ/yosys/master/techlibs/ice40/cells_sim.v
+`define SB_DFF_REG reg Q = 0
+
+module SB_DFF (output `SB_DFF_REG, input C, D);
+	always @(posedge C)
+		Q <= D;
+endmodule

tests/test_functional_tester.py

@@ -7,14 +7,6 @@
 import shutil
 
 
-def setup_function():
-    os.mkdir("tests/build")
-
-
-def teardown_function():
-    shutil.rmtree("tests/build")
-
-
 def test_configuration():
     class ConfigurationTester(FunctionalTester):
         def configure(self, addr, data):

tests/test_include_verilog.py

@@ -0,0 +1,23 @@
+import fault
+import magma as m
+import shutil
+
+
+def test_include_verilog():
+    SB_DFF = m.DeclareCircuit('SB_DFF', "D", m.In(m.Bit), "Q", m.Out(m.Bit),
+                              "C", m.In(m.Clock))
+    main = m.DefineCircuit('main', "I", m.In(m.Bit), "O", m.Out(m.Bit),
+                           *m.ClockInterface())
+    ff = SB_DFF()
+    m.wire(ff.D, main.I)
+    m.wire(ff.Q, main.O)
+    m.EndDefine()
+
+    tester = fault.Tester(main, main.CLK)
+    tester.poke(main.I, 1)
+    tester.eval()
+    tester.expect(main.O, 0)
+    tester.step(2)
+    tester.expect(main.O, 1)
+    tester.compile_and_run(target="verilator", directory="tests/build",
+                           include_verilog_files=["../sb_dff_sim.v"])