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// From https://raw.githubusercontent.com/YosysHQ/yosys/master/techlibs/ice40/cells_sim.v | ||
`define SB_DFF_REG reg Q = 0 | ||
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module SB_DFF (output `SB_DFF_REG, input C, D); | ||
always @(posedge C) | ||
Q <= D; | ||
endmodule |
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import pathlib | ||
import tempfile | ||
import fault | ||
import magma as m | ||
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def test_include_verilog(): | ||
SB_DFF = m.DeclareCircuit('SB_DFF', "D", m.In(m.Bit), "Q", m.Out(m.Bit), | ||
"C", m.In(m.Clock)) | ||
main = m.DefineCircuit('main', "I", m.In(m.Bit), "O", m.Out(m.Bit), | ||
*m.ClockInterface()) | ||
ff = SB_DFF() | ||
m.wire(ff.D, main.I) | ||
m.wire(ff.Q, main.O) | ||
m.EndDefine() | ||
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tester = fault.Tester(main, main.CLK) | ||
tester.poke(main.I, 1) | ||
tester.eval() | ||
tester.expect(main.O, 0) | ||
tester.step(2) | ||
tester.expect(main.O, 1) | ||
sb_dff_filename = pathlib.Path("tests/sb_dff_sim.v").resolve() | ||
with tempfile.TemporaryDirectory() as tmp_dir: | ||
tester.compile_and_run(target="verilator", directory=tmp_dir, | ||
include_verilog_files=[sb_dff_filename]) |