Wrap expression in parens

leonardt · May 24, 2019 · 78d3b1d · 78d3b1d
1 parent 40712c6
commit 78d3b1d
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py
@@ -108,7 +108,7 @@ def process_value(self, port, value):
                 new_value += "[0]"
             value = new_value
         elif isinstance(value, expression.Expression):
-            value = self.compile_expression(port, value)
+            value = f"({self.compile_expression(port, value)})"
         return value
 
     def compile_expression(self, port, value):