Fix style

leonardt · May 15, 2019 · a17e725 · a17e725
1 parent cddea7d
commit a17e725
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py
@@ -60,7 +60,7 @@ def __init__(self, circuit, circuit_name=None, directory="build/",
 
         magma_opts: Options dictionary for `magma.compile` command
 
-        simulator: "ncsim" or "vcs"
+        simulator: "ncsim", "vcs", or "iverilog"
 
         timescale: Set the timescale for the verilog simulation
                    (default 1ns/1ns)