Fixup test logic

leonardt · May 20, 2019 · b701243 · b701243
1 parent 4319b57
commit b701243
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Showing 3 changed files with 12 additions and 12 deletions.
diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py
@@ -286,14 +286,14 @@ def run(self, actions):
                                     capture_output=True)
         elif self.simulator == "iverilog":
             result = subprocess.run(f"vvp -N {self.circuit_name}_tb",
-                                    cwd=self.directory, shell=True)
+                                    cwd=self.directory, shell=True,
+                                    capture_output=True)
         if self.simulator in {"vcs", "iverilog"}:
-            assert not result.returncode, \
-                f"Running {self.simulator} binary failed"
             # VCS and iverilog do not set the return code when a
             # simulation exits with an error, so we check the result
             # of stdout to see if "Error" is present
-            if result.stdout:
-                print(result.stdout.decode())
-                assert "Error" not in str(result.stdout), \
-                    f"\"Error\" found during {self.simulator} run"
+            print(result.stdout.decode())
+            assert not result.returncode, \
+                f"Running {self.simulator} binary failed"
+            assert "Error" not in str(result.stdout), \
+                f"\"Error\" found in stdout of {self.simulator} run"
diff --git a/tests/common.py b/tests/common.py
@@ -20,7 +20,7 @@ def definition(io):
 TestBasicCircuit = define_simple_circuit(m.Bit, "BasicCircuit")
 TestArrayCircuit = define_simple_circuit(m.Array[3, m.Bit], "ArrayCircuit")
 TestByteCircuit = define_simple_circuit(m.Bits[8], "ByteCircuit")
-TestSIntCircuit = define_simple_circuit(m.SInt[3], "SIntCircuit")
+TestSIntCircuit = define_simple_circuit(m.SInt[4], "SIntCircuit")
 TestNestedArraysCircuit = define_simple_circuit(m.Array[3, m.Bits[4]],
                                                 "NestedArraysCircuit")
 TestDoubleNestedArraysCircuit = define_simple_circuit(

diff --git a/tests/test_tester.py b/tests/test_tester.py
@@ -351,16 +351,16 @@ def test_sint_circuit(target, simulator):
     circ = common.TestSIntCircuit
     tester = fault.Tester(circ)
 
-    inputs = [hwtypes.SIntVector.random(3) for _ in range(10)]
+    inputs = [hwtypes.SIntVector.random(4) for _ in range(10)]
 
     # have at least a few negative tests
     while sum(bool(x < 0) for x in inputs) < 3:
-        inputs = [hwtypes.SIntVector.random(3) for _ in range(10)]
+        inputs = [hwtypes.SIntVector.random(4) for _ in range(10)]
 
     for i in range(10):
-        tester.circuit.I = inputs[i]
+        tester.circuit.I = int(inputs[i])
         tester.eval()
-        tester.circuit.O.expect(inputs[i])
+        tester.circuit.O.expect(int(inputs[i]))
     with tempfile.TemporaryDirectory() as _dir:
         kwargs = {"target": target, "directory": _dir}
         if target == "system-verilog":