Refactor test circuits

Factor out common circuits into tests/common.py. Furthermore, each of
these circuits are just simple pass through circuits, so there is a
common generator for all of them (with type T as a paramter).

Also some other minor changes.

tests/common.py

@@ -1,9 +1,21 @@
 import magma as m
 
 
-class TestNestedArraysCircuit(m.Circuit):
-    IO = ["I", m.In(m.Array(3, m.Bits(4))), "O", m.Out(m.Array(3, m.Bits(4)))]
+def define_simple_circuit(T, circ_name, has_clk=False):
+    class _Circuit(m.Circuit):
+        name = circ_name
+        IO = ["I", m.In(T), "O", m.Out(T)]
+        if has_clk:
+            IO += ["CLK", m.In(m.Clock)]
 
-    @classmethod
-    def definition(io):
-        m.wire(io.I, io.O)
+        @classmethod
+        def definition(io):
+            m.wire(io.I, io.O)
+
+    return _Circuit
+
+
+TestBasicCircuit = define_simple_circuit(m.Bit, "BasicCircuit")
+TestNestedArraysCircuit = define_simple_circuit(m.Array(3, m.Bits(4)),
+                                                "NestedArraysCircuit")
+TestBasicClkCircuit = define_simple_circuit(m.Bit, "BasicClkCircuit", True)

tests/test_tester.py

@@ -6,10 +6,7 @@
 
 
 def test_tester_basic():
-    circ = m.DefineCircuit("test_circuit", "I", m.In(m.Bit), "O",
-                           m.Out(m.Bit))
-    m.wire(circ.I, circ.O)
-    m.EndDefine()
+    circ = common.TestBasicCircuit
     tester = fault.Tester(circ)
     tester.poke(circ.I, 0)
     tester.expect(circ.O, 0)
@@ -20,10 +17,7 @@ def test_tester_basic():
 
 
 def test_tester_clock():
-    circ = m.DefineCircuit("test_circuit_clock", "I", m.In(m.Bit), "O",
-                           m.Out(m.Bit), "CLK", m.In(m.Clock))
-    m.wire(circ.I, circ.O)
-    m.EndDefine()
+    circ = common.TestBasicClkCircuit
     tester = fault.Tester(circ, circ.CLK)
     tester.poke(circ.I, 0)
     tester.expect(circ.O, 0)

tests/test_verilator_target.py

@@ -6,26 +6,19 @@
 import random
 
 
-def test_verilator_target():
+def test_verilator_target_basic():
     """
     Test basic verilator workflow with a simple circuit.
     """
-
-    class Foo(m.Circuit):
-        IO = ["I", m.In(m.Bit), "O", m.Out(m.Bit)]
-
-        @classmethod
-        def definition(io):
-            m.wire(io.I, io.O)
-
+    circ = common.TestBasicCircuit
     with tempfile.TemporaryDirectory() as tempdir:
         # Compile to verilog.
         # TODO(rsetaluri): Make this part of the target itself.
-        m.compile(f"{tempdir}/Foo", Foo, output="verilog")
+        m.compile(f"{tempdir}/{circ.name}", circ, output="coreir-verilog")
 
         test_vectors = [[BitVector(0, 1), BitVector(0, 1)]]
         target = fault.verilator_target.VerilatorTarget(
-            Foo, test_vectors, directory=f"{tempdir}/")
+            circ, test_vectors, directory=f"{tempdir}/")
         target.run()