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Merge 6a4ffdf into 5d3ad36
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rsetaluri committed Jul 20, 2018
2 parents 5d3ad36 + 6a4ffdf commit d3f1c1e
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39 changes: 39 additions & 0 deletions fault/python_simulator_target.py
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from .target import Target
from magma.testing.function import testvectors
import magma.config as config
import inspect
import os
import subprocess
import magma as m
from magma.simulator.python_simulator import PythonSimulator


class PythonSimulatorTarget(Target):
def __init__(self, circuit, test_vectors, clock):
super().__init__(circuit, test_vectors)
self._clock = clock

def run(self):
ports = self._circuit.interface.ports
simulator = PythonSimulator(self._circuit, self._clock)
test_vector_length = len(self._test_vectors[0])
assert len(ports.keys()) == test_vector_length
clock_val = None
for tv_index, tv in enumerate(self._test_vectors):
for i, (name, port) in enumerate(ports.items()):
val = tv[i]
if port is self._clock:
if tv_index == 0:
clock_val = val
elif val != clock_val:
print("Advancing clock")
simulator.advance(2)
elif port.isoutput():
print(f"Setting {self._circuit.name}.{name} to {val}")
simulator.set_value(port, val)
elif port.isinput():
print(f"Asserting {self._circuit.name}.{name} is {val}")
sim_val = simulator.get_value(port)
assert sim_val == val
else:
raise NotImplementedError()
29 changes: 29 additions & 0 deletions tests/test_python_simulator_target.py
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import tempfile
import magma as m
import fault.python_simulator_target
from bit_vector import BitVector
import mantle


def test_python_simulator_target():
"""
Test basic python simulator workflow with a simple circuit.
"""

class Foo(m.Circuit):
IO = ["I", m.In(m.Bit), "O", m.Out(m.Bit)]

@classmethod
def definition(io):
m.wire(io.I, io.O)

def bit(val):
return BitVector(val, 1)

test_vectors = [
[bit(0), bit(0)],
[bit(1), bit(1)],
]
target = fault.python_simulator_target.PythonSimulatorTarget(
Foo, test_vectors, None)
target.run()

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