Merge 251a0e3 into fd70199

fault/system_verilog_target.py

@@ -12,7 +12,6 @@
 
 src_tpl = """\
 module {circuit_name}_tb;
-integer __error_occurred = 0;
 {declarations}
 
     {circuit_name} dut (
@@ -21,12 +20,7 @@
 
     initial begin
 {initial_body}
-        #20 begin
-            if (__error_occurred)
-                $stop;
-            else
-                $finish;
-        end;
+        #20 $finish;
     end
 
 endmodule
@@ -54,7 +48,7 @@ def __init__(self, circuit, circuit_name=None, directory="build/",
 
         magma_opts: Options dictionary for `magma.compile` command
 
-        simulator: "ncsim" or "vcs"
+        simulator: "ncsim", "vcs", or "iverilog"
 
         timescale: Set the timescale for the verilog simulation
                    (default 1ns/1ns)
@@ -187,7 +181,6 @@ def make_expect(self, i, action):
         return f"""
 if ({name} != {value}) begin
     $error(\"Failed on action={i} checking port {debug_name}. Expected %x, got %x\" , {value}, {name});
-    __error_occurred |= 1;
 end;
 """.splitlines()  # noqa
 
@@ -300,8 +293,15 @@ def run(self, actions):
         print(f"Running command: {cmd}")
         assert not subprocess.call(cmd, cwd=self.directory, shell=True)
         if self.simulator == "vcs":
-            print(f"Running command: {cmd}")
-            assert not subprocess.call("./simv", cwd=self.directory, shell=True)
+            # VCS doesn't set the return code when a simulation exits with an
+            # error, so we check the result of stdout to see if "Error" is
+            # present
+            result = subprocess.run("./simv", cwd=self.directory, shell=True,
+                                    capture_output=True)
+            print(result.stdout.decode())
+            assert not result.returncode, "Running vcs binary failed"
+            assert "Error" not in str(result.stdout), \
+                "String \"Error\" found in stdout of vcs run"
         elif self.simulator == "iverilog":
             assert not subprocess.call(f"vvp -N {self.circuit_name}_tb",
                                        cwd=self.directory, shell=True)

fault/verilator_target.py

@@ -376,8 +376,8 @@ def run(self, actions, verilator_includes=[], num_tests=0,
             self.circuit_name)
         assert not self.run_from_directory(verilator_make_cmd)
         assert not self.run_from_directory(
-            f"./obj_dir/V{self.circuit_name} | tee "
-            f"./obj_dir/{self.circuit_name}.log")
+            f"/bin/bash -c \"set -e -o pipefail; ./obj_dir/V{self.circuit_name}"
+            f" | tee ./obj_dir/{self.circuit_name}.log\"")
 
     def add_assumptions(self, circuit, actions, i):
         main_body = ""

tests/test_tester.py

@@ -7,6 +7,7 @@
 import tempfile
 import os
 import shutil
+import pytest
 
 
 def pytest_generate_tests(metafunc):
@@ -56,6 +57,21 @@ def test_tester_basic(target, simulator):
     assert tester.actions == []
 
 
+@pytest.mark.xfail(strict=True)
+def test_tester_basic_fail(target, simulator):
+    circ = common.TestBasicCircuit
+    tester = fault.Tester(circ)
+    tester.zero_inputs()
+    tester.poke(circ.I, 1)
+    tester.eval()
+    tester.expect(circ.O, 0)
+    with tempfile.TemporaryDirectory() as _dir:
+        if target == "verilator":
+            tester.compile_and_run(target, directory=_dir, flags=["-Wno-fatal"])
+        else:
+            tester.compile_and_run(target, directory=_dir, simulator=simulator)
+
+
 def test_tester_clock(target, simulator):
     circ = common.TestPeekCircuit
     tester = fault.Tester(circ)

tests/test_verilog_target.py

@@ -121,9 +121,9 @@ def test_target_clock(capfd, target, simulator):
             assert lines[-5] == "0", out
             assert lines[-4] == "1", out
         elif simulator == "vcs":
+            assert lines[-10] == "0", out
             assert lines[-9] == "0", out
-            assert lines[-8] == "0", out
-            assert lines[-7] == "1", out
+            assert lines[-8] == "1", out
         else:
             raise NotImplementedError(f"Unsupported simulator: {simulator}")
 
@@ -148,7 +148,7 @@ def test_print_nested_arrays(capfd, target, simulator):
         if simulator == "ncsim":
             actual = "\n".join(out.splitlines()[-9 - 3: -3])
         elif simulator == "vcs":
-            actual = "\n".join(out.splitlines()[-9 - 6: -6])
+            actual = "\n".join(out.splitlines()[-9 - 7: -7])
         else:
             raise NotImplementedError(f"Unsupported simulator: {simulator}")
     assert actual == """\
@@ -186,7 +186,7 @@ def test_print_double_nested_arrays(capfd, target, simulator):
         if simulator == "ncsim":
             actual = "\n".join(out.splitlines()[-18 - 3: -3])
         elif simulator == "vcs":
-            actual = "\n".join(out.splitlines()[-18 - 6: -6])
+            actual = "\n".join(out.splitlines()[-18 - 7: -7])
         else:
             raise NotImplementedError(f"Unsupported simulator: {simulator}")
     assert actual == """\