Update internal signal poking for MLIR

[leonardt]

The hack to poke an internal verilog signal corresponding to a coreir register no longer works: https://github.com/leonardt/fault/blob/master/fault/wrapper.py#L141-L147

Need to refer to the generated MLIR name (could insert a name in fault).

[rsetaluri]

It's actually not a backend issue since we still elaborate those registers within magma. So the following can work:

diff --git a/tests/test_setattr_interface.py b/tests/test_setattr_interface.py
index d892733..548aad2 100644
--- a/tests/test_setattr_interface.py
+++ b/tests/test_setattr_interface.py
@@ -77,7 +77,7 @@ def test_tester_poke_internal_register(target, simulator, capsys):
     tester.step(2)
     tester.print(TEST_START + '\n')
     for i in reversed(range(4)):
-        tester.circuit.config_reg.conf_reg.value = i
+        tester.circuit.config_reg.conf_reg.reg_P2_inst0 = i
         tester.step(2)
         tester.circuit.config_reg.conf_reg.O.expect(i)
         tester.print("O=%d\n", tester.circuit.config_reg.conf_reg.O)
``