Use ifelse pattern

leonardt · Oct 18, 2019 · 66a81be · 66a81be
1 parent 6609343
commit 66a81be
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Showing 5 changed files with 205 additions and 187 deletions.
diff --git a/jtag/compile.py b/jtag/compile.py
@@ -601,10 +601,12 @@ def compile(file):
         regs_str += f"reg {width}{r};\n"
 
     case_str = ""
-    case_str += "case (state)\n"
-    for case, transitions in case_map.items():
-        case_str += "    "
-        case_str += f"{case}: "
+    # case_str += "case (state)\n"
+    for i, (case, transitions) in enumerate(case_map.items()):
+        # case_str += "    "
+        if i > 0:
+            case_str += "end else "
+        case_str += f"if (state == {case}) begin\n    "
         for transition in transitions:
             if transition != transitions[0]:
                 case_str += " else "
@@ -628,8 +630,9 @@ def compile(file):
 
             case_str += f"    end"
         case_str += "\n"
-    case_str += "endcase"
-    case_str = "   " + "\n    ".join(line for line in case_str.splitlines())
+    case_str += "end"
+    # case_str += "endcase"
+    case_str = "    " + "\n    ".join(line for line in case_str.splitlines())
 
     # Assumes first state is first key
 
@@ -656,7 +659,7 @@ def compile(file):
     end
 end
 always @(*) begin
-  {case_str}
+{case_str}
 end
 endmodule
     """

diff --git a/jtag/fsm.blif b/jtag/fsm.blif
@@ -7,34 +7,34 @@
 .names $true
 1
 .names $undef
+.gate SB_LUT4 I0=curr_state[1] I1=curr_state[2] I2=$false I3=$false O=$abc$2616$new_n19_
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
+.param LUT_INIT 0100
 .gate SB_LUT4 I0=tms I1=curr_state[0] I2=curr_state[1] I3=curr_state[2] O=next_state[2]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
 .param LUT_INIT 1100111100001010
-.gate SB_LUT4 I0=curr_state[0] I1=tms I2=curr_state[3] I3=$abc$773$new_n27_ O=next_state[3]
+.gate SB_LUT4 I0=curr_state[0] I1=tms I2=curr_state[3] I3=$abc$2616$new_n19_ O=next_state[3]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
 .param LUT_INIT 0011011111110000
-.gate SB_LUT4 I0=curr_state[1] I1=curr_state[2] I2=$false I3=$false O=$abc$773$new_n27_
-.attr module_not_derived 00000000000000000000000000000001
-.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
-.param LUT_INIT 0100
-.gate SB_LUT4 I0=curr_state[0] I1=curr_state[3] I2=curr_state[1] I3=tms O=$abc$773$new_n29_
+.gate SB_LUT4 I0=curr_state[3] I1=curr_state[1] I2=curr_state[2] I3=tms O=$abc$2616$new_n24_
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
-.param LUT_INIT 1000111101110001
-.gate SB_LUT4 I0=tms I1=$abc$773$new_n29_ I2=curr_state[2] I3=$false O=next_state[1]
+.param LUT_INIT 1011001100001111
+.gate SB_LUT4 I0=tms I1=$abc$2616$new_n24_ I2=curr_state[0] I3=$false O=next_state[0]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
-.param LUT_INIT 11000101
-.gate SB_LUT4 I0=curr_state[3] I1=curr_state[1] I2=curr_state[2] I3=tms O=$abc$773$new_n31_
+.param LUT_INIT 11001010
+.gate SB_LUT4 I0=curr_state[0] I1=curr_state[3] I2=curr_state[1] I3=tms O=$abc$2616$new_n26_
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
-.param LUT_INIT 1011001100001111
-.gate SB_LUT4 I0=tms I1=$abc$773$new_n31_ I2=curr_state[0] I3=$false O=next_state[0]
+.param LUT_INIT 1000111101110001
+.gate SB_LUT4 I0=tms I1=$abc$2616$new_n26_ I2=curr_state[2] I3=$false O=next_state[1]
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
-.param LUT_INIT 11001010
+.param LUT_INIT 11000101
 .gate SB_DFFS C=CLK D=next_state[0] Q=curr_state[0] S=RESET
 .attr module_not_derived 00000000000000000000000000000001
 .attr src "fsm.v:10|/usr/local/bin/../share/yosys/ice40/cells_map.v:18"