Add jtag test

leonardt · Oct 16, 2019 · a4341dd · a4341dd
1 parent 7e1f1a5
commit a4341dd
Show file tree

Hide file tree

Showing 4 changed files with 193 additions and 3 deletions.
diff --git a/jtag/compile.py b/jtag/compile.py
@@ -452,14 +452,18 @@ def compile(file):
                 case_str += " else "
             cond = " && ".join(transition[1])
             case_str += f"if ({cond}) begin\n"
-            case_str += f"        state <= {transition[0]}\n"
+            case_str += f"        state <= {transition[0]};\n"
             case_str += f"    end"
         case_str += "\n"
     case_str += "endcase"
     case_str = "   " + "\n    ".join(line for line in case_str.splitlines())
+
+    # Assumes first state is first key
+    init = list(case_map.keys())[0]
+
     module_tmpl = f"""
 module {name}({io_str}, input CLK);
-reg [{state_width - 1}:0] state;
+reg [{state_width - 1}:0] state = {init};
 always @(posedge CLK) begin
 {case_str}
 end

diff --git a/jtag/fsm.py b/jtag/fsm.py
@@ -61,7 +61,7 @@ def capture(self):
     def shift(self):
         while True:
             tms = yield self.encodings["shift"]
-            if tms == 0:
+            if tms == 1:
                 yield from self.exit_1()
                 return
 

diff --git a/jtag/reference.v b/jtag/reference.v
@@ -0,0 +1,44 @@
+module tap(input tms, output [3:0] state, input CLK);
+  localparam TEST_LOGIC_RESET = 4'd15 ,
+             RUN_TEST_IDLE = 4'd12 ,
+             SELECT_DR_SCAN = 4'd7 ,
+             CAPTURE_DR = 4'd6 ,
+             SHIFT_DR = 4'd2 ,
+             EXIT1_DR = 4'd1 ,
+             PAUSE_DR = 4'd3 ,
+             EXIT2_DR = 4'd0 ,
+             UPDATE_DR = 4'd5 ,
+             SELECT_IR_SCAN = 4'd4 ,
+             CAPTURE_IR = 4'd14 ,
+             SHIFT_IR = 4'd10 ,
+             EXIT1_IR = 4'd9 ,
+             PAUSE_IR = 4'd11 ,
+             EXIT2_IR = 4'd8 ,
+             UPDATE_IR = 4'd13;
+  reg [3:0] CS = TEST_LOGIC_RESET;
+  reg [3:0] NS;
+  assign state = CS;
+  always @(posedge CLK) begin
+    CS <= NS;
+  end
+  always @(*) begin
+    case(CS)
+      TEST_LOGIC_RESET : NS = tms ? TEST_LOGIC_RESET : RUN_TEST_IDLE;
+      RUN_TEST_IDLE : NS = tms ? SELECT_DR_SCAN : RUN_TEST_IDLE ;
+      SELECT_DR_SCAN : NS = tms ? SELECT_IR_SCAN : CAPTURE_DR ;
+      CAPTURE_DR : NS = tms ? EXIT1_DR : SHIFT_DR ;
+      SHIFT_DR : NS = tms ? EXIT1_DR : SHIFT_DR ;
+      EXIT1_DR : NS = tms ? UPDATE_DR : PAUSE_DR ;
+      PAUSE_DR : NS = tms ? EXIT2_DR : PAUSE_DR ;
+      EXIT2_DR : NS = tms ? UPDATE_DR : SHIFT_DR ;
+      UPDATE_DR : NS = tms ? SELECT_DR_SCAN : RUN_TEST_IDLE ;
+      SELECT_IR_SCAN : NS = tms ? TEST_LOGIC_RESET : CAPTURE_IR ;
+      CAPTURE_IR : NS = tms ? EXIT1_IR : SHIFT_IR ;
+      SHIFT_IR : NS = tms ? EXIT1_IR : SHIFT_IR ;
+      EXIT1_IR : NS = tms ? UPDATE_IR : PAUSE_IR ;
+      PAUSE_IR : NS = tms ? EXIT2_IR : PAUSE_IR ;
+      EXIT2_IR : NS = tms ? UPDATE_IR : SHIFT_IR ;
+      UPDATE_IR : NS = tms ? SELECT_IR_SCAN : RUN_TEST_IDLE ;
+    endcase
+  end
+endmodule
diff --git a/jtag/test.py b/jtag/test.py
@@ -0,0 +1,142 @@
+import logging
+logging.basicConfig(level=logging.DEBUG)
+import fault
+import magma as m
+
+
+TEST_LOGIC_RESET = 15
+RUN_TEST_IDLE = 12
+SELECT_DR_SCAN = 7
+CAPTURE_DR = 6
+SHIFT_DR = 2
+EXIT1_DR = 1
+PAUSE_DR = 3
+EXIT2_DR = 0
+UPDATE_DR = 5
+SELECT_IR_SCAN = 4
+CAPTURE_IR = 14
+SHIFT_IR = 10
+EXIT1_IR = 9
+PAUSE_IR = 11
+EXIT2_IR = 8
+UPDATE_IR = 13
+
+circ = m.DefineFromVerilogFile("fsm.v", type_map={"CLK": m.In(m.Clock)})[0]
+tester = fault.Tester(circ, circ.CLK)
+tester.circuit.tms = 1
+tester.step(2)
+tester.circuit.state.expect(TEST_LOGIC_RESET)
+tester.circuit.tms = 1
+tester.step(2)
+tester.circuit.state.expect(TEST_LOGIC_RESET)
+
+tester.circuit.tms = 0
+tester.step(2)
+tester.circuit.state.expect(RUN_TEST_IDLE)
+
+tester.step(2)
+tester.circuit.state.expect(RUN_TEST_IDLE)
+
+tester.circuit.tms = 1
+tester.step(2)
+tester.circuit.state.expect(SELECT_DR_SCAN)
+
+tester.circuit.tms = 0
+tester.step(2)
+tester.circuit.state.expect(CAPTURE_DR)
+
+tester.circuit.tms = 1
+tester.step(2)
+tester.circuit.state.expect(EXIT1_DR)
+
+tester.circuit.tms = 0
+tester.step(2)
+tester.circuit.state.expect(PAUSE_DR)
+
+tester.circuit.tms = 0
+tester.step(2)
+tester.circuit.state.expect(PAUSE_DR)
+
+tester.circuit.tms = 1
+tester.step(2)
+tester.circuit.state.expect(EXIT2_DR)
+
+tester.circuit.tms = 0
+tester.step(2)
+tester.circuit.state.expect(SHIFT_DR)
+
+tester.circuit.tms = 0
+tester.step(2)
+tester.circuit.state.expect(SHIFT_DR)
+
+tester.circuit.tms = 0
+tester.step(2)
+tester.circuit.state.expect(SHIFT_DR)
+
+tester.circuit.tms = 1
+tester.step(2)
+tester.circuit.state.expect(EXIT1_DR)
+
+tester.circuit.tms = 1
+tester.step(2)
+tester.circuit.state.expect(UPDATE_DR)
+
+tester.circuit.tms = 1
+tester.step(2)
+tester.circuit.state.expect(SELECT_DR_SCAN)
+
+tester.circuit.tms = 1
+tester.step(2)
+tester.circuit.state.expect(SELECT_IR_SCAN)
+
+# BEGIN REPEAT FOR IR
+tester.circuit.tms = 0
+tester.step(2)
+tester.circuit.state.expect(CAPTURE_IR)
+
+tester.circuit.tms = 1
+tester.step(2)
+tester.circuit.state.expect(EXIT1_IR)
+
+tester.circuit.tms = 0
+tester.step(2)
+tester.circuit.state.expect(PAUSE_IR)
+
+tester.circuit.tms = 0
+tester.step(2)
+tester.circuit.state.expect(PAUSE_IR)
+
+tester.circuit.tms = 1
+tester.step(2)
+tester.circuit.state.expect(EXIT2_IR)
+
+tester.circuit.tms = 0
+tester.step(2)
+tester.circuit.state.expect(SHIFT_IR)
+
+tester.circuit.tms = 0
+tester.step(2)
+tester.circuit.state.expect(SHIFT_IR)
+
+tester.circuit.tms = 0
+tester.step(2)
+tester.circuit.state.expect(SHIFT_IR)
+
+tester.circuit.tms = 1
+tester.step(2)
+tester.circuit.state.expect(EXIT1_IR)
+
+tester.circuit.tms = 1
+tester.step(2)
+tester.circuit.state.expect(UPDATE_IR)
+# END REPEAT FOR IR
+
+tester.circuit.tms = 0
+tester.step(2)
+tester.circuit.state.expect(RUN_TEST_IDLE)
+
+tester.compile_and_run("verilator", magma_output="verilog")
+ref = m.DefineFromVerilogFile("reference.v", type_map={"CLK": m.In(m.Clock)})[0]
+
+ref_tester = tester.retarget(ref, ref.CLK)
+ref_tester.compile_and_run("verilator", magma_output="verilog")