Add chisel jtag

leonardt · Oct 16, 2019 · ada7c21 · ada7c21
1 parent fde4e49
commit ada7c21
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Showing 7 changed files with 366 additions and 18 deletions.
diff --git a/jtag/chisel.v b/jtag/chisel.v
diff --git a/jtag/compile.py b/jtag/compile.py
@@ -451,8 +451,10 @@ def compile(file):
             if transition != transitions[0]:
                 case_str += " else "
             cond = " && ".join(transition[1])
-            case_str += f"if ({cond}) begin\n"
-            case_str += f"        state <= {transition[0]};\n"
+            if transition != transitions[-1]:
+                case_str += f"if ({cond}) "
+            case_str += "begin\n"
+            case_str += f"        next_state = {transition[0]};\n"
             case_str += f"    end"
         case_str += "\n"
     case_str += "endcase"
@@ -462,10 +464,20 @@ def compile(file):
     init = list(case_map.keys())[0]
 
     module_tmpl = f"""
-module {name}({io_str}, input CLK);
-reg [{state_width - 1}:0] state = {init};
-always @(posedge CLK) begin
-{case_str}
+module {name}({io_str}, input CLK, input RESET);
+reg [{state_width - 1}:0] curr_state;
+reg [{state_width - 1}:0] next_state;
+assign state = curr_state;
+
+always @(posedge CLK or posedge RESET) begin
+    if (RESET) begin
+        curr_state <= {init};
+    end else begin
+        curr_state <= next_state;
+    end
+end
+always @(*) begin
+  {case_str}
 end
 endmodule
     """

diff --git a/jtag/evaluate.py b/jtag/evaluate.py
@@ -29,7 +29,7 @@ def evaluate_circuit(verilog_file, top_name):
     results[top_name]["LCs"] = 0
     results[top_name]["PLBs"] = 0
 
-    num_trials = 5
+    num_trials = 1
     for i in range(0, num_trials):
         res = run(f"yosys -p 'synth_ice40 -top {top_name} -blif {verilog_file}.blif' {verilog_file}.v | grep -A 20 \"2.44. Printing statistics.\"")
         for line in res.out.splitlines():
@@ -89,3 +89,5 @@ def evaluate_circuit(verilog_file, top_name):
 evaluate_circuit("fsm", "fsm")
 
 evaluate_circuit("reference", "tap")
+
+evaluate_circuit("chisel", "JtagStateMachine")
diff --git a/jtag/fsm.py b/jtag/fsm.py
@@ -6,10 +6,10 @@ class TAP(FSM):
     outputs = {"state": State}
 
     def __init__(self):
-        self.ir_scan = Scan(self, capture=14, shift=10, exit_1=9, pause=11,
-                            exit_2=8, update=13)
         self.dr_scan = Scan(self, capture=6, shift=2, exit_1=1, pause=3,
                             exit_2=0, update=5)
+        self.ir_scan = Scan(self, capture=14, shift=10, exit_1=9, pause=11,
+                            exit_2=8, update=13)
 
     def __call__(self):
         yield from self.test_logic_reset()

diff --git a/jtag/reference.v b/jtag/reference.v
@@ -1,4 +1,4 @@
-module tap(input tms, output [3:0] state, input CLK);
+module tap(input tms, output [3:0] state, input CLK, input RESET);
   localparam TEST_LOGIC_RESET = 4'd15 ,
              RUN_TEST_IDLE = 4'd12 ,
              SELECT_DR_SCAN = 4'd7 ,
@@ -15,11 +15,15 @@ module tap(input tms, output [3:0] state, input CLK);
              PAUSE_IR = 4'd11 ,
              EXIT2_IR = 4'd8 ,
              UPDATE_IR = 4'd13;
-  reg [3:0] CS = TEST_LOGIC_RESET;
+  reg [3:0] CS;
   reg [3:0] NS;
   assign state = CS;
-  always @(posedge CLK) begin
-    CS <= NS;
+  always @(posedge CLK, posedge RESET) begin
+    if (RESET) begin
+      CS <= TEST_LOGIC_RESET;
+    end else begin
+      CS <= NS;
+    end
   end
   always @(*) begin
     case(CS)
@@ -38,7 +42,7 @@ module tap(input tms, output [3:0] state, input CLK);
       EXIT1_IR : NS = tms ? UPDATE_IR : PAUSE_IR ;
       PAUSE_IR : NS = tms ? EXIT2_IR : PAUSE_IR ;
       EXIT2_IR : NS = tms ? UPDATE_IR : SHIFT_IR ;
-      UPDATE_IR : NS = tms ? SELECT_IR_SCAN : RUN_TEST_IDLE ;
+      UPDATE_IR : NS = tms ? SELECT_DR_SCAN : RUN_TEST_IDLE ;
     endcase
   end
 endmodule
diff --git a/jtag/results.json b/jtag/results.json
@@ -0,0 +1,56 @@
+{
+    "fsm": {
+        "SB_CARRY": 0,
+        "SB_DFF": 4,
+        "SB_LUT4": 7,
+        "logic levels": 2,
+        "path delay": 2.65,
+        "Max Clock Freq": 377.94,
+        "LCs": 7,
+        "PLBs": 1,
+        "wires": "9",
+        "wire bits": "18",
+        "public wires": "6",
+        "public wire bits": "15",
+        "memories": "0",
+        "memory bits": "0",
+        "processes": "0",
+        "cells": "11"
+    },
+    "tap": {
+        "SB_CARRY": 0,
+        "SB_DFF": 4,
+        "SB_LUT4": 7,
+        "logic levels": 2,
+        "path delay": 2.65,
+        "Max Clock Freq": 377.94,
+        "LCs": 7,
+        "PLBs": 1,
+        "wires": "9",
+        "wire bits": "18",
+        "public wires": "6",
+        "public wire bits": "15",
+        "memories": "0",
+        "memory bits": "0",
+        "processes": "0",
+        "cells": "11"
+    },
+    "JtagStateMachine": {
+        "SB_CARRY": 0,
+        "SB_DFF": 4,
+        "SB_LUT4": 9,
+        "logic levels": 2,
+        "path delay": 2.67,
+        "Max Clock Freq": 374.96,
+        "LCs": 9,
+        "PLBs": 2,
+        "wires": "100",
+        "wire bits": "176",
+        "public wires": "95",
+        "public wire bits": "171",
+        "memories": "0",
+        "memory bits": "0",
+        "processes": "0",
+        "cells": "13"
+    }
+}
diff --git a/jtag/test.py b/jtag/test.py
@@ -21,9 +21,16 @@
 EXIT2_IR = 8
 UPDATE_IR = 13
 
-circ = m.DefineFromVerilogFile("fsm.v", type_map={"CLK": m.In(m.Clock)})[0]
+circ = m.DefineFromVerilogFile("fsm.v", type_map={"CLK": m.In(m.Clock),
+                                                  "RESET": m.In(m.Reset)})[0]
 tester = fault.Tester(circ, circ.CLK)
 tester.circuit.tms = 1
+tester.circuit.RESET = 0
+tester.eval()
+tester.circuit.RESET = 1
+tester.eval()
+tester.circuit.RESET = 0
+tester.eval()
 tester.step(2)
 tester.circuit.state.expect(TEST_LOGIC_RESET)
 tester.circuit.tms = 1
@@ -131,12 +138,42 @@
 tester.circuit.state.expect(UPDATE_IR)
 # END REPEAT FOR IR
 
-tester.circuit.tms = 0
+tester.circuit.tms = 1
 tester.step(2)
-tester.circuit.state.expect(RUN_TEST_IDLE)
+tester.circuit.state.expect(SELECT_DR_SCAN)
+
+tester.circuit.tms = 1
+tester.step(2)
+tester.circuit.state.expect(SELECT_IR_SCAN)
+
+tester.circuit.tms = 1
+tester.step(2)
+tester.circuit.state.expect(TEST_LOGIC_RESET)
 
 tester.compile_and_run("verilator", magma_output="verilog")
-ref = m.DefineFromVerilogFile("reference.v", type_map={"CLK": m.In(m.Clock)})[0]
+ref = m.DefineFromVerilogFile("reference.v",
+                              type_map={"CLK": m.In(m.Clock),
+                                        "RESET": m.In(m.Reset)})[0]
 
 ref_tester = tester.retarget(ref, ref.CLK)
 ref_tester.compile_and_run("verilator", magma_output="verilog")
+
+chisel_ref = m.DefineFromVerilogFile("chisel.v",
+                                     type_map={"clk": m.In(m.Clock),
+                                               "reset": m.In(m.Reset)},
+                                     target_modules=["JtagStateMachine"])[0]
+
+class ChiselWrapper(m.Circuit):
+    IO = ["CLK", m.In(m.Clock), "tms", m.In(m.Bit), "state", m.Out(m.Bits[4]),
+          "RESET", m.In(m.Reset)]
+    @classmethod
+    def definition(io):
+        fsm = chisel_ref()
+        fsm.clock <= io.CLK
+        fsm.reset <= io.RESET
+        fsm.io_tms <= io.tms
+        io.state <= fsm.io_currState
+
+
+chisel_tester = tester.retarget(ChiselWrapper, ChiselWrapper.CLK)
+chisel_tester.compile_and_run("verilator", magma_output="verilog")