Merge 398f7bf into cc2699b

silica/cfg/control_flow_graph.py

@@ -221,7 +221,7 @@ def __init__(self, tree, width_table, func_locals, func_globals, sub_coroutines)
         # self.paths = promote_live_variables(self.paths)
         liveness_analysis(self)
         # render_paths_between_yields(self.paths)
-        self.ssa_var_to_curr_id_map = convert_to_ssa(self)
+        # self.ssa_var_to_curr_id_map = convert_to_ssa(self)
         # self.render()
         self.states, self.state_vars = build_state_info(self.paths, outputs, inputs)
 
@@ -467,9 +467,9 @@ def add_new_yield(self, value, output_map={}, array_stores_to_process=[]):
 
         self.add_new_block()
 
-    def add_new_branch(self, cond):
+    def add_new_branch(self, if_node):
         """
-        Adds a new ``Branch`` node with the condition ``cond`` to the CFG and
+        Adds a new ``Branch`` node with the if_node ``if_node`` to the CFG and
         connects the current block to it
 
         Generates a new ``BasicBlock`` corresponding to the True edge of the
@@ -480,7 +480,7 @@ def add_new_branch(self, cond):
         """
         old_block = self.curr_block
         # First we create an explicit branch node
-        self.curr_block = Branch(cond)
+        self.curr_block = Branch(if_node)
         self.blocks.append(self.curr_block)
         add_edge(old_block, self.curr_block)
         branch = self.curr_block
@@ -496,7 +496,7 @@ def process_branch(self, stmt):
         # orig_index_map = copy(self.replacer.index_map)
         # Emit new blocks for the branching instruction
         # self.replacer.visit(stmt.test)
-        branch = self.add_new_branch(stmt.test)
+        branch = self.add_new_branch(stmt)
         orig_bb = self.curr_block
         # true_stores = set()
         # for sub_stmt in stmt.body:

silica/cfg/types.py

@@ -65,9 +65,10 @@ def __iter__(self):
 
 
 class Branch(Block):
-    def __init__(self, cond):
+    def __init__(self, orig_node):
         super().__init__()
-        self.cond = cond
+        self.orig_node = orig_node
+        self.cond = orig_node.test
         self.true_edge = None
         self.false_edge = None
 

silica/compile.py

@@ -64,7 +64,7 @@ def add_coroutine_to_tables(coroutine, width_table, type_table, sub_coroutine_na
             type_table[output] = to_type_str(type_)
 
 
-def compile(coroutine, file_name=None, mux_strategy="one-hot", output='verilog', strategy="by_statement"):
+def compile(coroutine, file_name=None, mux_strategy="one-hot", output='verilog', strategy="by_path"):
     if not isinstance(coroutine, Coroutine):
         raise ValueError("silica.compile expects a silica.Coroutine")
 
@@ -235,10 +235,17 @@ def get_len(t):
             continue
         if isinstance(width, MemoryType):
             ctx.declare_reg(register, width.width, width.height)
+            ctx.declare_reg(register + "_next", width.width, width.height)
         else:
             ctx.declare_reg(register, width)
+            ctx.declare_reg(register + "_next", width)
 
-    init_body = [ctx.assign(ctx.get_by_name(key), value) for key,value in initial_values.items() if value is not None]
+    init_body = []
+    for key, value in initial_values.items():
+        if value is not None:
+            init_body.append(ctx.assign(ctx.get_by_name(key), value))
+            if key in registers:
+                init_body.append(ctx.assign(ctx.get_by_name(key + "_next"), value))
 
     # for sub_coroutine in sub_coroutines:
     #     for key, type_ in sub_coroutines[sub_coroutine].interface.ports.items():
@@ -279,8 +286,12 @@ def get_len(t):
     wens = {}
     # if initial_basic_block:
     #     states = states[1:]
-    verilog.compile_states(ctx, states, cfg.curr_yield_id == 3, width_table,
-                           registers, sub_coroutines, strategy)
+    if strategy == "by_statement":
+        verilog.compile_states(ctx, states, cfg.curr_yield_id == 3, width_table,
+                               registers, sub_coroutines)
+    else:
+        verilog.compile_by_path(ctx, cfg.paths, cfg.curr_yield_id == 3, width_table,
+                                registers, sub_coroutines, strategy)
     # cfg.render()
     verilog_str = ""
     for sub_coroutine in sub_coroutines.values():