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Fix missing package
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@leonardt
leonardt committed Oct 18, 2019
1 parent 7338135 commit e30f37f
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Showing 4 changed files with 52 additions and 43 deletions.
2 changes: 1 addition & 1 deletion jtag/compile.py
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Original file line number Diff line number Diff line change
Expand Up @@ -472,7 +472,7 @@ def compile(file):
desugar_for_loops(tree)
# print(astor.to_sourme(tree))
cfg = CFGBuilder().build(name, tree)
# cfg.build_visual(name, 'pdf')
cfg.build_visual(name, 'pdf')
num_yields = sum(count_yields(s) for s in cfg.entryblock.statements)
func_to_paths_map = build_func_to_paths_map(cfg)
join_yield_froms(func_to_paths_map)
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72 changes: 40 additions & 32 deletions jtag/fsm.v
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Original file line number Diff line number Diff line change
@@ -1,96 +1,104 @@

module fsm(input tms, output [3:0] state, input CLK, input RESET);


reg [3:0] curr_state;
reg [3:0] next_state;
assign state = curr_state;


always @(posedge CLK or posedge RESET) begin
if (RESET) begin
curr_state <= 15;

end else begin
curr_state <= next_state;
end
end
always @(*) begin
case (state)
15: if ((tms == 0)) begin
15: if (tms == 0) begin
next_state = 12;
end else begin
end else if ((tms != 0)) begin
next_state = 15;
end
12: if ((tms == 1)) begin
12: if (tms == 1) begin
next_state = 7;
end else begin
end else if ((tms != 1)) begin
next_state = 12;
end
7: if ((tms == 1)) begin
7: if (tms == 1) begin
next_state = 4;
end else begin
end else if ((tms != 1)) begin
next_state = 6;
end
4: if ((tms == 1)) begin
4: if (tms == 1) begin
next_state = 15;
end else begin
end else if ((tms != 1)) begin
next_state = 14;
end
6: if ((tms == 1)) begin
6: if (tms == 1) begin
next_state = 1;
end else begin
end else if ((tms != 1)) begin
next_state = 2;
end
2: if ((tms == 1)) begin
2: if (tms == 1) begin
next_state = 1;
end else begin
end else if ((tms != 1)) begin
next_state = 2;
end
1: if ((tms == 0)) begin
1: if (tms == 0) begin
next_state = 3;
end else begin
end else if (tms == 0) begin
next_state = 0;
end else if ((tms != 0)) begin
next_state = 5;
end
5: if ((tms == 1)) begin
5: if (tms == 1) begin
next_state = 7;
end else begin
end else if ((tms != 1)) begin
next_state = 12;
end
3: if ((tms == 0)) begin
3: if (tms == 0) begin
next_state = 3;
end else begin
end else if () begin
next_state = 0;
end
0: if ((tms == 0)) begin
0: if (tms == 0) begin
next_state = 2;
end else begin
end else if ((tms != 0)) begin
next_state = 5;
end
14: if ((tms == 1)) begin
14: if (tms == 1) begin
next_state = 9;
end else begin
end else if ((tms != 1)) begin
next_state = 10;
end
10: if ((tms == 1)) begin
10: if (tms == 1) begin
next_state = 9;
end else begin
end else if ((tms != 1)) begin
next_state = 10;
end
9: if ((tms == 0)) begin
9: if (tms == 0) begin
next_state = 11;
end else begin
end else if (tms == 0) begin
next_state = 8;
end else if ((tms != 0)) begin
next_state = 13;
end
13: if ((tms == 1)) begin
13: if (tms == 1) begin
next_state = 7;
end else begin
end else if ((tms != 1)) begin
next_state = 12;
end
11: if ((tms == 0)) begin
11: if (tms == 0) begin
next_state = 11;
end else begin
end else if () begin
next_state = 8;
end
8: if ((tms == 0)) begin
8: if (tms == 0) begin
next_state = 10;
end else begin
end else if ((tms != 0)) begin
next_state = 13;
end
endcase
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18 changes: 9 additions & 9 deletions sdram/fsm.py
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Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,7 @@ class SDRAM(FSM):
"cmd": Bits[8]
}
registers = {
"i": Bits[3]
"_": Bits[3]
}

def __call__(self):
Expand All @@ -72,13 +72,13 @@ def init(self):
refresh_cnt, rd_enable, wr_enable = yield INIT_PRE1, CMD_PALL
refresh_cnt, rd_enable, wr_enable = yield INIT_NOP1_1, CMD_NOP
refresh_cnt, rd_enable, wr_enable = yield INIT_REF1, CMD_REF
for i in range(7, -1, -1):
for _ in range(7, -1, -1):
refresh_cnt, rd_enable, wr_enable = yield INIT_NOP2, CMD_NOP
refresh_cnt, rd_enable, wr_enable = yield INIT_REF2, CMD_REF
for i in range(7, -1, -1):
for _ in range(7, -1, -1):
refresh_cnt, rd_enable, wr_enable = yield INIT_NOP3, CMD_NOP
refresh_cnt, rd_enable, wr_enable = yield INIT_LOAD, CMD_MRS
for i in range(2, -1, -1):
for _ in range(2, -1, -1):
refresh_cnt, rd_enable, wr_enable = yield INIT_NOP4, CMD_NOP
yield from self.idle()

Expand All @@ -95,25 +95,25 @@ def refresh(self):
refresh_cnt, rd_enable, wr_enable = yield REF_PRE, CMD_PALL
refresh_cnt, rd_enable, wr_enable = yield REF_NOP1, CMD_NOP
refresh_cnt, rd_enable, wr_enable = yield REF_REF, CMD_REF
for i in range(8, -1, -1):
for _ in range(8, -1, -1):
refresh_cnt, rd_enable, wr_enable = yield REF_NOP2, CMD_NOP
yield from self.idle()

def write(self):
refresh_cnt, rd_enable, wr_enable = yield WRIT_ACT, CMD_BACT
for i in range(2, -1, -1):
for _ in range(2, -1, -1):
refresh_cnt, rd_enable, wr_enable = yield WRIT_NOP1, CMD_NOP
refresh_cnt, rd_enable, wr_enable = yield WRIT_CAS, CMD_WRIT
for i in range(2, -1, -1):
for _ in range(2, -1, -1):
refresh_cnt, rd_enable, wr_enable = yield WRIT_NOP2, CMD_NOP
yield from self.idle()

def read(self):
refresh_cnt, rd_enable, wr_enable = yield READ_ACT, CMD_BACT
for i in range(2, -1, -1):
for _ in range(2, -1, -1):
refresh_cnt, rd_enable, wr_enable = yield READ_NOP1, CMD_NOP
refresh_cnt, rd_enable, wr_enable = yield READ_CAS, CMD_READ
for i in range(2, -1, -1):
for _ in range(2, -1, -1):
refresh_cnt, rd_enable, wr_enable = yield READ_NOP2, CMD_NOP
refresh_cnt, rd_enable, wr_enable = yield READ_READ, CMD_NOP
yield from self.idle()
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3 changes: 2 additions & 1 deletion setup.py
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Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@
description='',
packages=["silica", "silica.cfg"],
install_requires=[
"orderedset"
"orderedset",
"python-constraint"
]
)

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