Merge branch 'master' into verilog-backend

.coveragerc

@@ -0,0 +1,5 @@
+[run]
+omit =
+    silica/_config.py
+    silica/_testing.py
+    silica/magma_compile.py

.travis.yml

@@ -4,8 +4,11 @@ python:
 
 addons:
   apt:
+    sources:
+      - ubuntu-toolchain-r-test
     packages:
       - verilator
+      - g++-4.9
 
 before_install:
   # BEGIN: coreir installation
@@ -18,8 +21,13 @@ before_install:
 
 install:
   - pip install -r requirements.txt
+  - pip install python-coveralls
   - pip install pytest pytest-cov
 
 script:
   - pip install -e .
-  - pytest --cov=silica --doctest-modules
+  - pytest --cov=silica
+
+
+after_success:
+    - coveralls

README.md

@@ -1,5 +1,6 @@
 # Silica
 [![Build Status](https://travis-ci.org/leonardt/silica.svg?branch=master)](https://travis-ci.org/leonardt/silica)
+[![Coverage Status](https://coveralls.io/repos/github/leonardt/silica/badge.svg?branch=master)](https://coveralls.io/github/leonardt/silica?branch=master)
 
 A language for constructing hardware finite state machines using coroutines.
 

conftest.py

@@ -16,4 +16,4 @@ def silica_test():
     magma_clear_circuit_cache()
     clear_cachedFunctions()
 
-    # os.system("rm -rf tests/build/*")
+    os.system("rm -rf tests/build/*")

setup.py

@@ -6,6 +6,6 @@
     description='',
     packages=["silica"],
     install_requires=[
-        "fault==0.24"
+        "fault==0.27"
     ]
 )

silica/magma_compile.py

@@ -1,3 +1,8 @@
+# **NOTE:** Support for this backend is not currently being maintained so does
+# not likely work in its current state.
+# TODO: If reviving this backend, please enable coverage checking in
+# `.coveragerc`
+
 import ast
 from silica.transformations.replace_assign_to_bits import replace_assign_to_bits
 from silica.transformations.specialize_arguments import specialize_arguments

tests/test_lbmem.py

@@ -7,12 +7,12 @@
 from common import evaluate_circuit
 
 
-@si.combinational
-def saturating_add(a : si.UInt(7), b : si.UInt(7), max_ : si.UInt(7)) -> si.UInt(7):
-    c = a + b
-    if c == max_:
-        c = 0
-    return c
+# @si.combinational
+# def saturating_add(a : si.UInt(7), b : si.UInt(7), max_ : si.UInt(7)) -> si.UInt(7):
+#     c = a + b
+#     if c == max_:
+#         c = 0
+#     return c
 
 
 @si.generator