couple of minor fixes. send_cnt was not being initialized in one of them

leonardt · Nov 8, 2018 · e6a3b32 · e6a3b32
1 parent 2695b2c
commit e6a3b32
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Showing 4 changed files with 5 additions and 9 deletions.
diff --git a/verilog/counter.v b/verilog/counter.v
@@ -2,7 +2,7 @@ module vcounter(input CLK, output [2:0] O);
 reg [2:0] O;
 
 always @(posedge CLK) begin
-    O <= O + 1;
+    O <= O + 1'b1;
 end
 
 endmodule
diff --git a/verilog/detect111.v b/verilog/detect111.v
@@ -3,7 +3,7 @@ module detect111(
   input I,
   output O
 );
-  reg [1:0] cnt = 0;
+  reg [1:0] cnt = 2'h0;
 
   wire [1:0] cnt_next;
 

diff --git a/verilog/lbmem.v b/verilog/lbmem.v
@@ -36,7 +36,7 @@ module lbmem(
 
   reg [5:0] waddr = 6'h0;
   wire [5:0] raddr;
-  assign raddr = waddr - {2'h0, wen ? cnt : cnt-1'b1};
+  assign raddr = waddr - {2'h0, (wen ? cnt : cnt-1'b1)};
 
   always @(posedge CLK) begin
     if (wen) begin

diff --git a/verilog/uart.v b/verilog/uart.v
@@ -1,6 +1,6 @@
 module uart_tx(input CLK, input [7:0] data, input valid, output tx, output ready);
     reg [7:0] message;
-    reg [2:0] send_cnt;
+    reg [2:0] send_cnt = 3'h0; //Was not initialized. 
     reg [1:0] state = 2'h0;
     always @(posedge CLK) begin
         case (state)
@@ -21,11 +21,7 @@ module uart_tx(input CLK, input [7:0] data, input valid, output tx, output ready
                     ready <= 1'b0;
                     tx <= message[send_cnt];
                     send_cnt <= send_cnt - 1'b1;
-                    if (send_cnt > 0) begin
-                        state <= 2'h1;
-                    end else begin
-                        state <= 2'h2;
-                    end
+                    state <= (send_cnt > 0) ? 2'h1 : 2'h2;
                 end
             2'h2:
                 begin