Remove code duplication in verilog detect

leonardt · Oct 19, 2018 · f0f0b0d · f0f0b0d
1 parent 741a5a2
commit f0f0b0d
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/tests/test_counter.py b/tests/test_counter.py
@@ -40,7 +40,7 @@ def test_counter():
     if __name__ == '__main__':
         m.compile("tests/build/mantle_counter", mantle_counter)
         print("===== BEGIN : SILICA RESULTS =====")
-        evaluate_circuit("counter_si", "SilicaCounter")
+        evaluate_circuit("counter_si", "counter")
         print("===== END   : SILICA RESULTS =====")
         print("===== BEGIN : MANTLE RESULTS =====")
         evaluate_circuit("mantle_counter", "Counter3")

diff --git a/verilog/detect111.v b/verilog/detect111.v
@@ -8,7 +8,7 @@ module detect111(
   wire [1:0] cnt_next;
 
   always @(posedge CLK) begin
-    cnt <= I ? (cnt==3 ? cnt : cnt+1) : 0;
+    cnt <= cnt_next;
   end
 
   // mealey version