Test cmd and fix output bug

leonardt · Oct 18, 2019 · f25ddaf · f25ddaf
1 parent 0871b55
commit f25ddaf
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Showing 2 changed files with 6 additions and 2 deletions.
diff --git a/jtag/compile.py b/jtag/compile.py
@@ -502,14 +502,14 @@ def compile(file):
                     is_yield(path[-1].statements[0]) and len(path) > 1:
                 if isinstance(path[0].statements[0].value.value, ast.Tuple):
                     start_state = path[0].statements[0].value.value.elts[0]
+                    if init_outputs is None:
+                        init_outputs = path[0].statements[0].value.value.elts[1:]
                     end_state = path[-1].statements[0].value.value.elts[0]
                     outputs = path[-1].statements[0].value.value.elts[1:]
                 else:
                     start_state = path[0].statements[0].value.value
                     end_state = path[-1].statements[0].value.value
                     outputs = []
-                if init_outputs is None:
-                    init_outputs = outputs
                 if isinstance(start_state, ast.Str):
                     assert isinstance(end_state, ast.Str)
                     start_state, end_state = start_state.s, end_state.s

diff --git a/sdram/test.py b/sdram/test.py
@@ -14,12 +14,16 @@
 tester.circuit.RESET = 0
 tester.eval()
 tester.circuit.state.expect(0b01000)
+tester.circuit.cmd.expect(0b10111000)
 tester.step(2)
 tester.circuit.state.expect(0b01001)
+tester.circuit.cmd.expect(0b10010001)
 tester.step(2)
 tester.circuit.state.expect(0b00101)
+tester.circuit.cmd.expect(0b10111000)
 tester.step(2)
 tester.circuit.state.expect(0b01010)
+tester.circuit.cmd.expect(0b10001000)
 tester.step(2)
 
 tester.compile_and_run("verilator", magma_output="verilog")