New ssa

[leonardt]

Works! Now implemented as a separate pass on the control flow graph. I think the logic is cleaner, but it's still quite complicated. There's some cleaning up of the output verilog that still needs to be done so we can evaluate with yosys (yosys needs "bulk" memory assignments to be unrolled so each element is assigned, that is data_2[0] = data_1[0] where data_1 and data_2 are 2d arrays.