Init SSA based verilog synthesis

[leonardt]

This uses a variant of SSA form to synthesize the corresponding hardware for the coroutine. This algorithm improves on the original by preserving a linear correspondence between code size and synthesized hardware. This pull request implements the necessary parts of the algorithm to implement our current set of test examples. Quality of the synthesized results has not been evaluated or optimized yet. Next steps include evaluation, optimizations, and clean up/refactor this code and add documentation.