Merge 55fc6a1 into 8578a85

include/verilogAST.hpp

@@ -319,6 +319,19 @@ class BlockComment : public StructuralStatement, public BehavioralStatement {
   ~BlockComment(){};
 };
 
+class InlineVerilog : public StructuralStatement {
+  // Serializes into `value`, so allows the inclusion of arbitrary verilog
+  // statement(s) in the body of a module definition.  The contents of
+  // `value` must be a valid verilog statement inside a module body.  The
+  // contents are not validated.
+ public:
+  std::string value;
+
+  InlineVerilog(std::string value) : value(value){};
+  std::string toString() { return value; };
+  ~InlineVerilog(){};
+};
+
 typedef std::vector<
     std::pair<std::unique_ptr<Identifier>, std::unique_ptr<Expression>>>
     Parameters;

tests/basic.cpp

@@ -395,6 +395,14 @@ TEST(BasicTests, Comment) {
   EXPECT_EQ(block_comment.toString(),
             "/*\nTest comment\non multiple lines\n*/");
 }
+TEST(BasicTests, InlineVerilog) {
+  vAST::InlineVerilog inline_verilog(
+      "logic [1:0] x;\n"
+      "assign x = 2'b10;\n");
+  EXPECT_EQ(inline_verilog.toString(),
+            "logic [1:0] x;\n"
+            "assign x = 2'b10;\n");
+}
 
 }  // namespace