Merge c08b7dd into 8b779ee

include/verilogAST.hpp

@@ -439,6 +439,33 @@ class BlockComment : public StructuralStatement, public BehavioralStatement {
   ~BlockComment(){};
 };
 
+class ExprComment : public Expression {
+ protected:
+  virtual ExprComment* clone_impl() const override {
+    return new ExprComment(this->expr->clone(), this->value);
+  };
+
+ public:
+  std::unique_ptr<Expression> expr;
+  std::string value;
+
+  ExprComment(std::unique_ptr<Expression> expr, std::string value)
+      : expr(std::move(expr)), value(value){};
+  std::string toString() override { return expr->toString() + "/*" + value + "*/"; };
+  ~ExprComment(){};
+};
+
+class PortComment : public AbstractPort {
+ public:
+  std::unique_ptr<Port> port;
+  std::string value;
+
+  PortComment(std::unique_ptr<AbstractPort> port, std::string value)
+      : port(std::move(port)), value(value){};
+  std::string toString() override { return port->toString() + "/*" + value + "*/"; };
+  ~PortComment(){};
+};
+
 class InlineVerilog : public StructuralStatement {
   // Serializes into `value`, so allows the inclusion of arbitrary verilog
   // statement(s) in the body of a module definition.  The contents of

tests/basic.cpp

@@ -427,6 +427,12 @@ TEST(BasicTests, Comment) {
   vAST::SingleLineComment stmt_with_comment("Test comment",
                                             std::move(cont_assign));
   EXPECT_EQ(stmt_with_comment.toString(), "assign a = b;  // Test comment");
+  vAST::ExprComment expr_comment(vAST::make_id("i"), "verilator_public");
+  EXPECT_EQ(expr_comment.toString(), "i/*verilator_public*/");
+  vAST::PortComment port_comment(
+      std::make_unique<vAST::Port>(vAST::make_id("i"), vAST::INPUT, vAST::WIRE),
+      "verilator_public");
+  EXPECT_EQ(port_comment.toString(), "input i/*verilator_public*/");
 }
 TEST(BasicTests, InlineVerilog) {
   vAST::InlineVerilog inline_verilog(