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Merge cde0b8d into 32d8f85
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leonardt committed Jul 9, 2019
2 parents 32d8f85 + cde0b8d commit 58e17bd
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Showing 3 changed files with 26 additions and 10 deletions.
24 changes: 17 additions & 7 deletions include/verilogAST.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -176,7 +176,9 @@ enum Direction { INPUT, OUTPUT, INOUT };
// TODO: Unify with declarations?
enum PortType { WIRE, REG };

class Port : public Node {
class AbstractPort : public Node {};

class Port : public AbstractPort {
// Required
// `<name>` or `<name>[n]` or `name[n:m]`
std::variant<Identifier *, Index *, Slice *> value;
Expand All @@ -195,6 +197,14 @@ class Port : public Node {
std::string toString();
};

class StringPort : public AbstractPort {
std::string value;

public:
StringPort(std::string value) : value(value){};
std::string toString() { return value; };
};

class Statement : public Node {};

class SingleLineComment : public Statement {
Expand Down Expand Up @@ -345,18 +355,17 @@ class AbstractModule : public Node {};
class Module : public AbstractModule {
protected:
std::string name;
std::vector<Port *> ports;
std::vector<AbstractPort *> ports;
std::vector<std::variant<StructuralStatement *, Declaration *>> body;
Parameters parameters;
std::string emitModuleHeader();
// Protected initializer that is used by the StringBodyModule subclass which
// overrides the `body` field (but reuses the other fields)
Module(std::string name, std::vector<Port *> ports,
Parameters parameters)
Module(std::string name, std::vector<AbstractPort *> ports, Parameters parameters)
: name(name), ports(ports), parameters(parameters){};

public:
Module(std::string name, std::vector<Port *> ports,
Module(std::string name, std::vector<AbstractPort *> ports,
std::vector<std::variant<StructuralStatement *, Declaration *>> body,
Parameters parameters)
: name(name), ports(ports), body(body), parameters(parameters){};
Expand All @@ -368,14 +377,15 @@ class StringBodyModule : public Module {
std::string body;

public:
StringBodyModule(std::string name, std::vector<Port *> ports, std::string body,
Parameters parameters)
StringBodyModule(std::string name, std::vector<AbstractPort *> ports,
std::string body, Parameters parameters)
: Module(name, ports, parameters), body(body){};
std::string toString();
};

class StringModule : public AbstractModule {
std::string definition;

public:
StringModule(std::string definition) : definition(definition){};
std::string toString() { return definition; };
Expand Down
10 changes: 8 additions & 2 deletions tests/basic.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -149,6 +149,12 @@ TEST(BasicTests, TestPort) {
EXPECT_EQ(o_reg_port.toString(), "output reg o");
}

TEST(BasicTests, TestStringPort) {
vAST::StringPort port("output reg [width-1:0] I");

EXPECT_EQ(port.toString(), "output reg [width-1:0] I");
}

TEST(BasicTests, TestModuleInst) {
std::string module_name = "test_module";

Expand Down Expand Up @@ -189,7 +195,7 @@ TEST(BasicTests, TestModule) {
vAST::Identifier o("o");
vAST::Port o_port(&o, vAST::OUTPUT, vAST::WIRE);

std::vector<vAST::Port *> ports = {&i_port, &o_port};
std::vector<vAST::AbstractPort *> ports = {&i_port, &o_port};

std::vector<std::variant<vAST::StructuralStatement *, vAST::Declaration *>>
body;
Expand Down Expand Up @@ -334,7 +340,7 @@ TEST(BasicTests, File) {
vAST::Identifier o("o");
vAST::Port o_port(&o, vAST::OUTPUT, vAST::WIRE);

std::vector<vAST::Port *> ports = {&i_port, &o_port};
std::vector<vAST::AbstractPort *> ports = {&i_port, &o_port};

std::vector<std::variant<vAST::StructuralStatement *, vAST::Declaration *>>
body;
Expand Down
2 changes: 1 addition & 1 deletion tests/parameterized_module.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,7 @@ TEST(ParameterizedModuleTests, TestEq) {
vAST::Port in1_port(&in1_slice, vAST::INPUT, vAST::WIRE);
vAST::Port out_port(&out, vAST::OUTPUT, vAST::WIRE);

std::vector<vAST::Port *> ports = {&in0_port, &in1_port, &out_port};
std::vector<vAST::AbstractPort *> ports = {&in0_port, &in1_port, &out_port};

std::vector<std::variant<vAST::StructuralStatement *, vAST::Declaration *>>
body;
Expand Down

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