Merge 53b0d06 into 244b2c5

include/verilogAST.hpp

@@ -178,10 +178,21 @@ enum PortType { WIRE, REG };
 
 class AbstractPort : public Node {};
 
+class Vector : public Node {
+  Identifier *id;
+  Expression *msb;
+  Expression *lsb;
+
+ public:
+  Vector(Identifier *id, Expression *msb, Expression *lsb)
+      : id(id), msb(msb), lsb(lsb){};
+  std::string toString() override;
+};
+
 class Port : public AbstractPort {
   // Required
   // `<name>` or `<name>[n]` or `name[n:m]`
-  std::variant<Identifier *, Index *, Slice *> value;
+  std::variant<Identifier *, Vector *> value;
 
   // technically the following are optional (e.g. port direction/data type
   // can be declared in the body of the definition), but for now let's force
@@ -191,7 +202,7 @@ class Port : public AbstractPort {
   PortType data_type;
 
  public:
-  Port(std::variant<Identifier *, Index *, Slice *> value, Direction direction,
+  Port(std::variant<Identifier *, Vector *> value, Direction direction,
        PortType data_type)
       : value(value), direction(direction), data_type(data_type){};
   std::string toString();
@@ -258,9 +269,9 @@ class ModuleInstantiation : public StructuralStatement {
 class Declaration : public Node {
  protected:
   std::string decl;
-  std::variant<Identifier *, Index *, Slice *> value;
+  std::variant<Identifier *, Vector *> value;
 
-  Declaration(std::variant<Identifier *, Index *, Slice *> value,
+  Declaration(std::variant<Identifier *, Vector *> value,
               std::string decl)
       : decl(decl), value(value){};
 
@@ -270,13 +281,13 @@ class Declaration : public Node {
 
 class Wire : public Declaration {
  public:
-  Wire(std::variant<Identifier *, Index *, Slice *> value)
+  Wire(std::variant<Identifier *, Vector *> value)
       : Declaration(value, "wire"){};
 };
 
 class Reg : public Declaration {
  public:
-  Reg(std::variant<Identifier *, Index *, Slice *> value)
+  Reg(std::variant<Identifier *, Vector *> value)
       : Declaration(value, "reg"){};
 };
 
@@ -361,7 +372,8 @@ class Module : public AbstractModule {
   std::string emitModuleHeader();
   // Protected initializer that is used by the StringBodyModule subclass which
   // overrides the `body` field (but reuses the other fields)
-  Module(std::string name, std::vector<AbstractPort *> ports, Parameters parameters)
+  Module(std::string name, std::vector<AbstractPort *> ports,
+         Parameters parameters)
       : name(name), ports(ports), parameters(parameters){};
 
  public:

src/verilogAST.cpp

@@ -35,6 +35,10 @@ std::string Slice::toString() {
          low_index->toString() + ']';
 }
 
+std::string Vector::toString() {
+  return "[" + msb->toString() + ':' + lsb->toString() + "] " + id->toString();
+}
+
 std::string BinaryOp::toString() {
   std::string op_str;
   switch (op) {
@@ -141,7 +145,7 @@ std::string variant_to_string(std::variant<Ts...> value) {
 
 std::string Port::toString() {
   std::string value_str =
-      variant_to_string<Identifier *, Index *, Slice *>(value);
+      variant_to_string<Identifier *, Vector *>(value);
   std::string direction_str;
   switch (direction) {
     case INPUT:

tests/basic.cpp

@@ -56,6 +56,14 @@ TEST(BasicTests, TestSlice) {
   EXPECT_EQ(slice.toString(), "x[32'd31:32'd0]");
 }
 
+TEST(BasicTests, TestVector) {
+  vAST::Identifier id("x");
+  vAST::NumericLiteral high("31");
+  vAST::NumericLiteral low("0");
+  vAST::Vector slice(&id, &high, &low);
+  EXPECT_EQ(slice.toString(), "[32'd31:32'd0] x");
+}
+
 TEST(BasicTests, TestBinaryOp) {
   std::vector<std::pair<vAST::BinOp::BinOp, std::string>> ops;
   ops.push_back(std::make_pair(vAST::BinOp::LSHIFT, "<<"));
@@ -266,16 +274,11 @@ TEST(BasicTests, TestDeclaration) {
   EXPECT_EQ(reg.toString(), "reg a;");
 
   vAST::Identifier id("x");
-  vAST::NumericLiteral n("0");
-  vAST::Index index(&id, &n);
-  vAST::Wire wire_index(&index);
-  EXPECT_EQ(wire_index.toString(), "wire x[32'd0];");
-
   vAST::NumericLiteral high("31");
   vAST::NumericLiteral low("0");
-  vAST::Slice slice(&id, &high, &low);
+  vAST::Vector slice(&id, &high, &low);
   vAST::Reg reg_slice(&slice);
-  EXPECT_EQ(reg_slice.toString(), "reg x[32'd31:32'd0];");
+  EXPECT_EQ(reg_slice.toString(), "reg [32'd31:32'd0] x;");
 }
 
 TEST(BasicTests, TestAssign) {

tests/parameterized_module.cpp

@@ -30,11 +30,11 @@ TEST(ParameterizedModuleTests, TestEq) {
   vAST::BinaryOp hi(&width,vAST::BinOp::SUB,&one);
   auto lo = zero;
 
-  vAST::Slice in0_slice(&in0, &hi, &lo);
-  vAST::Slice in1_slice(&in1, &hi, &lo);
+  vAST::Vector in0_vec(&in0, &hi, &lo);
+  vAST::Vector in1_vec(&in1, &hi, &lo);
 
-  vAST::Port in0_port(&in0_slice, vAST::INPUT, vAST::WIRE);
-  vAST::Port in1_port(&in1_slice, vAST::INPUT, vAST::WIRE);
+  vAST::Port in0_port(&in0_vec, vAST::INPUT, vAST::WIRE);
+  vAST::Port in1_port(&in1_vec, vAST::INPUT, vAST::WIRE);
   vAST::Port out_port(&out, vAST::OUTPUT, vAST::WIRE);
 
   std::vector<vAST::AbstractPort *> ports = {&in0_port, &in1_port, &out_port};
@@ -52,7 +52,7 @@ TEST(ParameterizedModuleTests, TestEq) {
 
   cout << "//coreir_eq" << endl << coreir_eq.toString() << endl;
   std::string expected_str =
-      "module coreir_eq #(parameter width = 32'd1) (input in0[width - 32'd1:32'd0], input in1[width - 32'd1:32'd0], output out);\n"
+      "module coreir_eq #(parameter width = 32'd1) (input [width - 32'd1:32'd0] in0, input [width - 32'd1:32'd0] in1, output out);\n"
       "assign out = in0 == in1;\n"
       "endmodule\n";
   EXPECT_EQ(coreir_eq.toString(), expected_str);