Inline assigns

[leonardt]

Adds initial support for inlining assignment statements.

There's probably more cases to consider, but I think this should be a start for the coreir verilog backend (inlining primitive expressions/wires).

Requires the addition of copy constructors and cloning unique ptr logic for Expressions (eventually we'll want to extend this to support all node types).

Adds basic logic for inlining continuous wire assignments. When a wire is only read once, it will be replaced with it's driver. If it's read more than once, it will only be replaced if it it's driven by another wire (so it won't propagate/duplicate expressions, just names)

Perhaps a better name for this is wire propagation?

[leonardt]

(Forgot to do a code cleanup pass before submitting, so I'll do that, but feel free to point out any suggestions on refactoring)

[leonardt]

Also, this requires that assignments are in topologically sorted order (not necessary in Verilog). Fortunately (for now), the corier backend emits the statements in this order, but to support more general trees in the future we could simply sort the statements first.