Add ability to include inline verilog

[leonardt]

Adds a node that serializes to it's value, which allows the passing of inline verilog through the compiler. This will enable the use of inline verilog in magma (ala pragma asm). For now magma (or fault rather) will be responsible for interpolating the verilog name in the inline verilog (e.g. referring to a tuple field will need to be mapped to the verilog name). We can work on more robust/extensible ways to handle this in the future.

[rsetaluri]

Is there any expectation/constraints on what value can correspond to? Like if I pass in an entire module declaration is that valid? Or only "body" stuff? Presumably this can't checked but it should be documented.

[leonardt]

I don't think we can validate the contents, but in terms of rules:

It can be used inside the body of a module definition, so any valid statement or collection of statements is valid. Technically it can also be used inside any always block, but that won't really matter for our current use case (since we'll just be using this to allow inline verilog like assertions inside a magma definition), later on we could also support inline expressions, but again I don't think that would be used in the current intended flow. For now, I'll change it to just Structural statement and document the intended use case.