Fix handling of multiple assignments in inlining

[leonardt]

This fixes a case where multiple assignments to a variable were not being treated properly in the nested blacklisting logic. Here's an example where this code:

module Mux2xArray3_Array2_OutBit (
    input [1:0] I0 [2:0],
    input [1:0] I1 [2:0],
    input S,
    output [1:0] O [2:0]
);
reg [5:0] coreir_commonlib_mux2x6_inst0_out_unq1;
wire [5:0] coreir_commonlib_mux2x6_inst0_in_data_0;
wire [5:0] coreir_commonlib_mux2x6_inst0_in_data_1;
wire [5:0] coreir_commonlib_mux2x6_inst0_out;
always @(*) begin
if (S == 0) begin
    coreir_commonlib_mux2x6_inst0_out_unq1 = coreir_commonlib_mux2x6_inst0_in_data_0;
end else begin
    coreir_commonlib_mux2x6_inst0_out_unq1 = coreir_commonlib_mux2x6_inst0_in_data_1;
end
end

assign coreir_commonlib_mux2x6_inst0_in_data_0 = {I0[2][1:0],I0[1][1:0],I0[0][1:0]};
assign coreir_commonlib_mux2x6_inst0_in_data_1 = {I1[2][1:0],I1[1][1:0],I1[0][1:0]};
assign coreir_commonlib_mux2x6_inst0_out = coreir_commonlib_mux2x6_inst0_out_unq1;
assign O[2] = coreir_commonlib_mux2x6_inst0_out_unq1[5:4];
assign O[1] = coreir_commonlib_mux2x6_inst0_out_unq1[3:2];
assign O[0] = coreir_commonlib_mux2x6_inst0_out_unq1[1:0];
endmodule

would turn into

module Mux2xArray3_Array2_OutBit (
    input [1:0] I0 [2:0],
    input [1:0] I1 [2:0],
    input S,
    output [1:0] O [2:0]
);
reg [5:0] coreir_commonlib_mux2x6_inst0_out_unq1;
wire [5:0] coreir_commonlib_mux2x6_inst0_in_data_1;
always @(*) begin
if (S == 0) begin
    coreir_commonlib_mux2x6_inst0_out_unq1 = {I0[2][1:0],I0[1][1:0],I0[0][1:0]};
end else begin
    coreir_commonlib_mux2x6_inst0_out_unq1 = coreir_commonlib_mux2x6_inst0_in_data_1;
end
end

assign coreir_commonlib_mux2x6_inst0_in_data_1 = {I1[2][1:0],I1[1][1:0],I1[0][1:0]};
assign O[2] = coreir_commonlib_mux2x6_inst0_out_unq1[5:4];
assign O[1] = coreir_commonlib_mux2x6_inst0_out_unq1[3:2];
assign O[0] = coreir_commonlib_mux2x6_inst0_out_unq1[1:0];
endmodule

Notice coreir_commonlib_mux2x6_inst0_in_data_1 isn't inlined, this is because it drives coreir_commonlib_mux2x6_inst0_out_unq1 which in turn drives a slice that shouldn't be inlined, so the recursive inline logic prevents it from being inlined.

However, it should see that coreir_commonlib_mux2x6_inst0_out_unq1 is assigned twice, so it won't be inlined, which then allows coreir_commonlib_mux2x6_inst0_in_data_1.

This change moves the assignment count logic up to the front to blacklist wires from being inlined if they're assigned more than once, than updates the recursive blacklisting logic to detect and stop when it encounters a wire that's already being blacklisted (which then allows other drivers to be inlined, rather than continuing to recurse).

Also adds a convenience construct to If when there are no else_ifs