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[STM32F3] Removed all specific F3 stuff out of common files.
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esden committed Jul 7, 2013
1 parent a1321fc commit ebb0588
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Showing 13 changed files with 352 additions and 215 deletions.
91 changes: 2 additions & 89 deletions include/libopencm3/stm32/common/spi_common_all.h
Expand Up @@ -129,33 +129,6 @@ specific memorymap.h header before including this header file.*/
/* CRCNEXT: Transmit CRC next */
#define SPI_CR1_CRCNEXT (1 << 12)

/* DFF: Data frame format */
/****************************************************************************/
/** @defgroup spi_dff SPI data frame format
@ingroup spi_defines
@{*/
#if defined(STM32F3)

#define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c)
#define SPI1_DR8 SPI_DR8(SPI1_BASE)
#define SPI2_DR8 SPI_DR8(SPI2_I2S_BASE)
#define SPI3_DR8 SPI_DR8(SPI3_I2S_BASE)

#define SPI_CR1_CRCL_8BIT (0 << 11)
#define SPI_CR1_CRCL_16BIT (1 << 11)
/**@}*/
#define SPI_CR1_CRCL (1 << 11)

#elif !defined(STM32F3)

#define SPI_CR1_DFF_8BIT (0 << 11)
#define SPI_CR1_DFF_16BIT (1 << 11)
/**@}*/
#define SPI_CR1_DFF (1 << 11)

#endif

/* RXONLY: Receive only */
#define SPI_CR1_RXONLY (1 << 10)

Expand Down Expand Up @@ -235,41 +208,7 @@ specific memorymap.h header before including this header file.*/

/* --- SPI_CR2 values ------------------------------------------------------ */

/* Bits [15:8]: Reserved. Forced to 0 by hardware. */

#if defined(STM32F3)

/* LDMA_TX: Last DMA transfer for transmission */
#define SPI_CR2_LDMA_TX (1 << 14)

/* LDMA_RX: Last DMA transfer for reception */
#define SPI_CR2_LDMA_RX (1 << 13)

/* FRXTH: FIFO reception threshold */
#define SPI_CR2_FRXTH (1 << 12)

/* DS [3:0]: Data size */
// 0x0 - 0x2 NOT USED
#define SPI_CR2_DS_4BIT (0x3 << 8)
#define SPI_CR2_DS_5BIT (0x4 << 8)
#define SPI_CR2_DS_6BIT (0x5 << 8)
#define SPI_CR2_DS_7BIT (0x6 << 8)
#define SPI_CR2_DS_8BIT (0x7 << 8)
#define SPI_CR2_DS_9BIT (0x8 << 8)
#define SPI_CR2_DS_10BIT (0x9 << 8)
#define SPI_CR2_DS_11BIT (0xA << 8)
#define SPI_CR2_DS_12BIT (0xB << 8)
#define SPI_CR2_DS_13BIT (0xC << 8)
#define SPI_CR2_DS_14BIT (0xD << 8)
#define SPI_CR2_DS_15BIT (0xE << 8)
#define SPI_CR2_DS_16BIT (0xF << 8)
#define SPI_CR2_DS_MASK (0xF << 8)


/* NSSP: NSS pulse management */
#define SPI_CR2_NSSP (1 << 3)

#endif
/* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */

/* TXEIE: Tx buffer empty interrupt enable */
#define SPI_CR2_TXEIE (1 << 7)
Expand All @@ -294,23 +233,7 @@ specific memorymap.h header before including this header file.*/

/* --- SPI_SR values ------------------------------------------------------- */

/* Bits [15:8]: Reserved. Forced to 0 by hardware. */

#if defined(STM32F3)

/* FTLVL[1:0]: FIFO Transmission Level */
#define SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11)
#define SPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11)
#define SPI_SR_FTLVL_HALF_FIFO (0x2 << 11)
#define SPI_SR_FTLVL_FIFO_FULL (0x3 << 11)

/* FRLVL[1:0]: FIFO Reception Level */
#define SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9)
#define SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9)
#define SPI_SR_FRLVL_HALF_FIFO (0x2 << 9)
#define SPI_SR_FRLVL_FIFO_FULL (0x3 << 9)

#endif
/* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */

/* BSY: Busy flag */
#define SPI_SR_BSY (1 << 7)
Expand Down Expand Up @@ -469,16 +392,6 @@ void spi_disable_tx_dma(uint32_t spi);
void spi_enable_rx_dma(uint32_t spi);
void spi_disable_rx_dma(uint32_t spi);

#ifdef STM32F3
void spi_set_data_size(uint32_t spi, uint16_t data_s);
void spi_fifo_reception_threshold_8bit(uint32_t spi);
void spi_fifo_reception_threshold_16bit(uint32_t spi);
void spi_i2s_mode_spi_mode(uint32_t spi);
void spi_send8(uint32_t spi, uint8_t data);
uint8_t spi_read8(uint32_t spi);

#endif

END_DECLS

/**@}*/
Expand Down
65 changes: 65 additions & 0 deletions include/libopencm3/stm32/common/spi_common_f0124.h
@@ -0,0 +1,65 @@
/** @addtogroup spi_defines
@author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/

/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H
The order of header inclusion is important. spi.h includes the device
specific memorymap.h header before including this header file.*/

/** @cond */
#ifdef LIBOPENCM3_SPI_H
/** @endcond */
#ifndef LIBOPENCM3_SPI_COMMON_F0124_H
#define LIBOPENCM3_SPI_COMMON_F0124_H

/**@{*/

#include <libopencm3/stm32/common/spi_common_all.h>

/*
* This file extends the common STM32 version with definitions only
* applicable to the STM32F0/1/2/4 series of devices.
*/

/* DFF: Data frame format */
/****************************************************************************/
/** @defgroup spi_dff SPI data frame format
@ingroup spi_defines
@{*/

#define SPI_CR1_DFF_8BIT (0 << 11)
#define SPI_CR1_DFF_16BIT (1 << 11)

/**@}*/

#define SPI_CR1_DFF (1 << 11)

#endif
/** @cond */
#else
#warning "spi_common_f24.h should not be included explicitly, only via spi.h"
#endif
/** @endcond */
/**@}*/

2 changes: 1 addition & 1 deletion include/libopencm3/stm32/common/spi_common_f24.h
Expand Up @@ -34,7 +34,7 @@ specific memorymap.h header before including this header file.*/

/**@{*/

#include <libopencm3/stm32/common/spi_common_all.h>
#include <libopencm3/stm32/common/spi_common_f0124.h>

/*
* This file extends the common STM32 version with definitions only
Expand Down
2 changes: 1 addition & 1 deletion include/libopencm3/stm32/f1/spi.h
Expand Up @@ -32,7 +32,7 @@ LGPL License Terms @ref lgpl_license
#define LIBOPENCM3_SPI_H

#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/spi_common_all.h>
#include <libopencm3/stm32/common/spi_common_f0124.h>

#endif

78 changes: 76 additions & 2 deletions include/libopencm3/stm32/f3/spi.h
Expand Up @@ -32,7 +32,81 @@ LGPL License Terms @ref lgpl_license
#define LIBOPENCM3_SPI_H

#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/spi_common_f24.h>
#include <libopencm3/stm32/common/spi_common_all.h>

#endif
/* DFF: Data frame format */
/****************************************************************************/
/** @defgroup spi_dff SPI data frame format
@ingroup spi_defines
@{*/

#define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c)
#define SPI1_DR8 SPI_DR8(SPI1_BASE)
#define SPI2_DR8 SPI_DR8(SPI2_I2S_BASE)
#define SPI3_DR8 SPI_DR8(SPI3_I2S_BASE)

#define SPI_CR1_CRCL_8BIT (0 << 11)
#define SPI_CR1_CRCL_16BIT (1 << 11)
/**@}*/
#define SPI_CR1_CRCL (1 << 11)

/* --- SPI_CR2 values ------------------------------------------------------ */

/* LDMA_TX: Last DMA transfer for transmission */
#define SPI_CR2_LDMA_TX (1 << 14)

/* LDMA_RX: Last DMA transfer for reception */
#define SPI_CR2_LDMA_RX (1 << 13)

/* FRXTH: FIFO reception threshold */
#define SPI_CR2_FRXTH (1 << 12)

/* DS [3:0]: Data size */
// 0x0 - 0x2 NOT USED
#define SPI_CR2_DS_4BIT (0x3 << 8)
#define SPI_CR2_DS_5BIT (0x4 << 8)
#define SPI_CR2_DS_6BIT (0x5 << 8)
#define SPI_CR2_DS_7BIT (0x6 << 8)
#define SPI_CR2_DS_8BIT (0x7 << 8)
#define SPI_CR2_DS_9BIT (0x8 << 8)
#define SPI_CR2_DS_10BIT (0x9 << 8)
#define SPI_CR2_DS_11BIT (0xA << 8)
#define SPI_CR2_DS_12BIT (0xB << 8)
#define SPI_CR2_DS_13BIT (0xC << 8)
#define SPI_CR2_DS_14BIT (0xD << 8)
#define SPI_CR2_DS_15BIT (0xE << 8)
#define SPI_CR2_DS_16BIT (0xF << 8)
#define SPI_CR2_DS_MASK (0xF << 8)

/* NSSP: NSS pulse management */
#define SPI_CR2_NSSP (1 << 3)

/* --- SPI_SR values ------------------------------------------------------- */

/* FTLVL[1:0]: FIFO Transmission Level */
#define SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11)
#define SPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11)
#define SPI_SR_FTLVL_HALF_FIFO (0x2 << 11)
#define SPI_SR_FTLVL_FIFO_FULL (0x3 << 11)

/* FRLVL[1:0]: FIFO Reception Level */
#define SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9)
#define SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9)
#define SPI_SR_FRLVL_HALF_FIFO (0x2 << 9)
#define SPI_SR_FRLVL_FIFO_FULL (0x3 << 9)

/* --- Function prototypes ------------------------------------------------- */

BEGIN_DECLS

void spi_set_data_size(uint32_t spi, uint16_t data_s);
void spi_fifo_reception_threshold_8bit(uint32_t spi);
void spi_fifo_reception_threshold_16bit(uint32_t spi);
void spi_i2s_mode_spi_mode(uint32_t spi);
void spi_send8(uint32_t spi, uint8_t data);
uint8_t spi_read8(uint32_t spi);

END_DECLS

#endif

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