SPI driver structure for L0 L1 F0 F1 F2 F4 #740
Comments
SevenW
changed the title
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As I understand, I think the current direction is to drop the "L1F124" naming when it gets to a certain point of complexity. ADC and USB do this by grouping into arbitrary "versions", such as "st_usbfs_v1" and "st_usbfs_v2". What are the registers "missing" from the low-end F1 and F0x0 chips you mention ? (note, I'm mostly a spectator in this project, I don't make decisions ! ) |
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I was in doubt on the _v2 naming convention. In two cases, the _v2 suffix is an addition to the original _common_all (adc, usbfs) and in one case it is a full replacement (usart). I will come back to the "reduced function" F1 and F0. |
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Missing from value line F0x0 and F100, with respect to other F0/F1: |
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it was my understanding that all L0 chips have the "spi v2+" peripheral, with the fifos, that comes in with f3 and f0. There's probably not a lot you want to try and get too common. Are you sure there's not a PR for spi on l0 already? |
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Is a PR a github "issue"? Could not find it. I have prepared and tested a L0 implementation. It is not a lot of change. I try to prepare a pull request tonight. (The only open question for me: should I rename spi_common_l1.h to spi_common_v2.h?) |
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A preview on my intended delta can be found here: |
split spi stuff in three part: - v1 : basic spi peripheral - v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr - v2 : spi with variable datasize, fifo and other fancy stuff. v1 maps to f1 chips v1_frf to f2, f4 and l0,l1 v2 to f0, f3 and l4 This breaks spi_master_init API for v2 devices : function prototype from common spi header used to be abused, with DFF bit reused for CRCL bit. New v2 spi_master_init does not handle anymore CRCL bits, as it does not usually mess with other crc configuration.
split spi stuff in three part: - v1 : basic spi peripheral - v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr - v2 : spi with variable datasize, fifo and other fancy stuff. v1 maps to f1 chips v1_frf to f2, f4 and l0,l1 v2 to f0, f3 and l4 This breaks spi_master_init API for v2 devices : function prototype from common spi header used to be abused, with DFF bit reused for CRCL bit. New v2 spi_master_init does not handle anymore CRCL bits, as it does not usually mess with other crc configuration.
split spi stuff in three part: - v1 : basic spi peripheral - v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr - v2 : spi with variable datasize, fifo and other fancy stuff. v1 maps to f1 chips v1_frf to f2, f4 and l0,l1 v2 to f0, f3 and l4 This breaks spi_master_init API for v2 devices : function prototype from common spi header used to be abused, with DFF bit reused for CRCL bit. New v2 spi_master_init does not handle anymore CRCL bits, as it does not usually mess with other crc configuration.
split spi stuff in three part: - v1 : basic spi peripheral - v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr - v2 : spi with variable datasize, fifo and other fancy stuff. v1 maps to f1 chips v1_frf to f2, f4 and l0,l1 v2 to f0, f3 and l4 This breaks spi_master_init API for v2 devices : function prototype from common spi header used to be abused, with DFF bit reused for CRCL bit. New v2 spi_master_init does not handle anymore CRCL bits, as it does not usually mess with other crc configuration.
split spi stuff in three part: - v1 : basic spi peripheral - v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr - v2 : spi with variable datasize, fifo and other fancy stuff. v1 maps to f1 chips v1_frf to f2, f4 and l0,l1 v2 to f0, f3 and l4 This breaks spi_master_init API for v2 devices : function prototype from common spi header used to be abused, with DFF bit reused for CRCL bit. New v2 spi_master_init does not handle anymore CRCL bits, as it does not usually mess with other crc configuration.
split spi stuff in three part: - v1 : basic spi peripheral - v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr - v2 : spi with variable datasize, fifo and other fancy stuff. v1 maps to f1 chips v1_frf to f2, f4 and l0,l1 v2 to f0, f3 and l4 This breaks spi_master_init API for v2 devices : function prototype from common spi header used to be abused, with DFF bit reused for CRCL bit. New v2 spi_master_init does not handle anymore CRCL bits, as it does not usually mess with other crc configuration.
split spi stuff in three part: - v1 : basic spi peripheral - v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr - v2 : spi with variable datasize, fifo and other fancy stuff. v1 maps to f1 chips v1_frf to f2, f4 and l0,l1 v2 to f0, f3 and l4 This breaks spi_master_init API for v2 devices : function prototype from common spi header used to be abused, with DFF bit reused for CRCL bit. New v2 spi_master_init does not handle anymore CRCL bits, as it does not usually mess with other crc configuration.
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tot he best of my knowledge this is closed now. new or extra or missing portions should come in as new tickets please. |
split spi stuff in three part: - v1 : basic spi peripheral - v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr - v2 : spi with variable datasize, fifo and other fancy stuff. v1 maps to f1 chips v1_frf to f2, f4 and l0,l1 v2 to f0, f3 and l4 This breaks spi_master_init API for v2 devices : function prototype from common spi header used to be abused, with DFF bit reused for CRCL bit. New v2 spi_master_init does not handle anymore CRCL bits, as it does not usually mess with other crc configuration.
split spi stuff in three part: - v1 : basic spi peripheral - v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr - v2 : spi with variable datasize, fifo and other fancy stuff. v1 maps to f1 chips v1_frf to f2, f4 and l0,l1 v2 to f0, f3 and l4 This breaks spi_master_init API for v2 devices : function prototype from common spi header used to be abused, with DFF bit reused for CRCL bit. New v2 spi_master_init does not handle anymore CRCL bits, as it does not usually mess with other crc configuration.
I am in the process of adding a STM32 L0 SPI driver. Once done, I like to make a pull request. I see a lot of similarity among the L's and F's, and now I am seeking advice on structuring the files, I compared "SPI register map" tables from various STM32 reference manuals. Compared to starting with spi_common_all.h the following types of STM32 add capabilities:
Note: some low budget mcu's F100, F0x0 have fewer registers then common_all. Missing two full registers (not only bits).
Observation on current implementation:
common_all < L1F124 < F24What I want to do is separate out L1 and make a common L01F24
Please advice on the naming of the spi_common_*.h
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