added rcc_hsi16_div4() and rcc_set_pll_source() for stm32l0 (tested) #609
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Correct, L0 support is very new |
| @@ -160,6 +160,8 @@ | |||
| #define RCC_CFGR_PLLMUL_MASK 0xf | |||
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| /* PLLSRC: PLL entry clock source */ | |||
| #define RCC_CFGR_PLLSRC_SHIFT 16 | |||
| #define RCC_CFGR_PLLSRC_MASK (1 << RCC_CFGR_PLLSRC_SHIFT) | |||
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no need for mask and shift definitions for single bits.
karlp
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Feb 24, 2018
reported by: kaeipnos in libopencm3#609
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pll source has landed, if people still want the div4 support we can make a new PR for that. |
BOJIT
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Jan 30, 2021
reported by: kaeipnos in libopencm3#609
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I started to use libopencm3 for a small project with an nucleo-L053R8 board, but It seems that some key functions were missing ( hsi16 divider and pll source switch ).
Of course those functions are trivial to implement but it makes source code a bit more readable.
It seems that stm32l0 targets aren't well supported.
I've also started a miniblink example for this board that uses those functions, and if you think it can be useful I can make another pull request on libopencm3-examples when it's ready.