FuseSoC cannot determine cores on the CI instance

[oleg-nenashev]

Expected behavior (local Machine)

MacBook-Pro-onenashev-2:fusesoc-icarus nenashev$ docker run -u 106:111 onenashev/fusesoc-icarus fusesoc sim wb_sdram_ctrl
Running FuseSoC in /fusesoc
Cloning into '/fusesoc/.local/share/orpsoc-cores'...
WARN:  Failed to register cores root '/fusesoc/.local/share/orpsoc-cores is not a directory'
INFO:  Initializing orpsoc-cores
INFO:  Writing configuration file to '/fusesoc/.config/fusesoc/fusesoc.conf'
INFO:  FuseSoC is ready to use!
Compiling /fusesoc/build/wb_sdram_ctrl/src/elf-loader/elf-loader.c...
Compiling /fusesoc/build/wb_sdram_ctrl/src/elf-loader/vpi_wrapper.c...
Making elf-loader.vpi from  elf-loader.o vpi_wrapper.o...
wb_sdram_ctrl_tb.masters[0].wb_bfm_transactor0 : Running 1000 transactions
Max burst length=5
wb_sdram_ctrl_tb.masters[1].wb_bfm_transactor0 : Running 1000 transactions
Max burst length=5
wb_sdram_ctrl_tb.masters[2].wb_bfm_transactor0 : Running 1000 transactions
Max burst length=5
wb_sdram_ctrl_tb.masters[0].wb_bfm_transactor0 : 0/1000
wb_sdram_ctrl_tb.masters[2].wb_bfm_transactor0 : 0/1000
wb_sdram_ctrl_tb.masters[1].wb_bfm_transactor0 : 0/1000
wb_sdram_ctrl_tb.masters[0].wb_bfm_transactor0 : 100/1000
wb_sdram_ctrl_tb.masters[2].wb_bfm_transactor0 : 100/1000
wb_sdram_ctrl_tb.masters[1].wb_bfm_transactor0 : 100/1000
wb_sdram_ctrl_tb.masters[0].wb_bfm_transactor0 : 200/1000
wb_sdram_ctrl_tb.masters[2].wb_bfm_transactor0 : 200/1000
wb_sdram_ctrl_tb.masters[1].wb_bfm_transactor0 : 200/1000
wb_sdram_ctrl_tb.masters[0].wb_bfm_transactor0 : 300/1000
wb_sdram_ctrl_tb.masters[2].wb_bfm_transactor0 : 300/1000
wb_sdram_ctrl_tb.masters[1].wb_bfm_transactor0 : 300/1000
wb_sdram_ctrl_tb.masters[0].wb_bfm_transactor0 : 400/1000
wb_sdram_ctrl_tb.masters[2].wb_bfm_transactor0 : 400/1000
wb_sdram_ctrl_tb.masters[1].wb_bfm_transactor0 : 400/1000
wb_sdram_ctrl_tb.masters[0].wb_bfm_transactor0 : 500/1000
wb_sdram_ctrl_tb.masters[2].wb_bfm_transactor0 : 500/1000
wb_sdram_ctrl_tb.masters[1].wb_bfm_transactor0 : 500/1000
wb_sdram_ctrl_tb.masters[0].wb_bfm_transactor0 : 600/1000
wb_sdram_ctrl_tb.masters[2].wb_bfm_transactor0 : 600/1000
wb_sdram_ctrl_tb.masters[1].wb_bfm_transactor0 : 600/1000
wb_sdram_ctrl_tb.masters[0].wb_bfm_transactor0 : 700/1000
wb_sdram_ctrl_tb.masters[2].wb_bfm_transactor0 : 700/1000
wb_sdram_ctrl_tb.masters[1].wb_bfm_transactor0 : 700/1000
wb_sdram_ctrl_tb.masters[0].wb_bfm_transactor0 : 800/1000
wb_sdram_ctrl_tb.masters[2].wb_bfm_transactor0 : 800/1000
wb_sdram_ctrl_tb.masters[1].wb_bfm_transactor0 : 800/1000
wb_sdram_ctrl_tb.masters[0].wb_bfm_transactor0 : 900/1000
wb_sdram_ctrl_tb.masters[2].wb_bfm_transactor0 : 900/1000
wb_sdram_ctrl_tb.masters[1].wb_bfm_transactor0 : 900/1000
Average wait times
Master 0 : 390970.000000
Master 1 : 406820.000000
Master 2 : 398920.000000
All tests passed!
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in stream_utils-1.0
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in elf-loader
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in vlog_tb_utils
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_altera_ddr_wrapper
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in fifo-1.0
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in ram_wb
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_intercon-1.0
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_intercon
WARN:  plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in wb_sdram_ctrl
INFO:  Preparing elf-loader
INFO:  Preparing wiredelay
INFO:  Preparing mt48lc16m16a2
INFO:  Checking out http://www.micron.com/~/media/Documents/Products/Sim%20Model/DRAM/DRAM/4012mt48lc16m16a2.zip to /fusesoc/cache/mt48lc16m16a2
INFO:  Preparing vlog_tb_utils-1.0
INFO:  Preparing wb_bfm
INFO:  Preparing wb_sdram_ctrl
INFO:  Downloading skristiansson/wb_sdram_ctrl from github

INFO:  Running /fusesoc/.local/share/orpsoc-cores/cores/elf-loader/check_libelf.sh

Actual behavior:

[Pipeline] withDockerContainer
$ docker run -t -d -u 106:111 -w /var/lib/jenkins/workspace/Infra/FuseSoC-Docker -v /var/lib/jenkins/workspace/Infra/FuseSoC-Docker:/var/lib/jenkins/workspace/Infra/FuseSoC-Docker:rw -v /var/lib/jenkins/workspace/Infra/FuseSoC-Docker@tmp:/var/lib/jenkins/workspace/Infra/FuseSoC-Docker@tmp:rw -e ******** -e ******** -e ******** -e ******** -e ******** -e ******** -e ******** -e ******** -e ******** -e ******** -e ******** -e ******** -e ******** -e ******** -e ******** -e ******** onenashev/fusesoc-icarus cat
[Pipeline] {
[Pipeline] sh
[FuseSoC-Docker] Running shell script
+ fusesoc init -y
�[1;33mWARN:  '/fusesoc/.local/share/orpsoc-cores' already exists�[0m
�[1;37mINFO:  Writing configuration file to '/fusesoc/.config/fusesoc/fusesoc.conf'�[0m
�[1;37mINFO:  FuseSoC is ready to use!�[0m
[Pipeline] sh
[FuseSoC-Docker] Running shell script
+ fusesoc list-cores

Available cores on the CI instance:

�[1;31mERROR: No cores found in /fusesoc/.local/share/orpsoc-cores:/fusesoc/systems�[0m
[Pipeline] }
$ docker stop f5d4d007ee87c27ed2ceb26b53e508234d051ae8a2958c476cc5ffddacb80805
$ docker rm -f f5d4d007ee87c27ed2ceb26b53e508234d051ae8a2958c476cc5ffddacb80805
[Pipeline] // withDockerContainer
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE

[oleg-nenashev]

After 85d6073 it happens due to the strange behavior of entrypoint within Docker Pipeline. Seems git checkout from it only inits repo and then escapes from the script.

Workaround - manual reinitialization of the repo:

fusesocIcarus.inside {
        sh "rm -rf orpsoc-cores"
        git 'https://github.com/openrisc/orpsoc-cores.git'
        sh 'fusesoc sim wb_sdram_ctrl'
}