directory_structure

master/comments branch

doc - Microarchitecture diagrams for all stages in XML format to be used with draw.io

emulator - C source used as test harness are fed to verilator to generate emulator

install - Compiled ISA/BENCHMARK tests

project - Scala configuration files fed to Scala Build Tool(sbt)

riscv-fesvr - Frontend Server for the target to load the binaries and execute any requested syscall. It is a forked version to add support for system-bus access

riscv-tests - Recipe to generate ISA/BENCHMARK tests

sbt - sbt_launch.jar which is fed to java to launch sbt

src - Scala Sources

vsrc - Verilog Sources used for blackbox in chisel

Makefile - To automate building the emulators

devel branch

fpga - TCL scripts to build bitstream for PYNQ-Z1

freechipsproject - Source files compiled, packaged and used as a library in the rest of the project