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hns_roce_u_hw_v2.c
2687 lines (2155 loc) · 67.3 KB
/
hns_roce_u_hw_v2.c
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/*
* Copyright (c) 2016-2017 Hisilicon Limited.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#define _GNU_SOURCE
#include <stdio.h>
#include <string.h>
#include <sys/mman.h>
#include <ccan/minmax.h>
#include "hns_roce_u.h"
#include "hns_roce_u_db.h"
#include "hns_roce_u_hw_v2.h"
#define HR_IBV_OPC_MAP(ib_key, hr_key) \
[IBV_WR_ ## ib_key] = HNS_ROCE_WQE_OP_ ## hr_key
static const uint32_t hns_roce_opcode[] = {
HR_IBV_OPC_MAP(RDMA_WRITE, RDMA_WRITE),
HR_IBV_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM),
HR_IBV_OPC_MAP(SEND, SEND),
HR_IBV_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM),
HR_IBV_OPC_MAP(RDMA_READ, RDMA_READ),
HR_IBV_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOMIC_COM_AND_SWAP),
HR_IBV_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOMIC_FETCH_AND_ADD),
HR_IBV_OPC_MAP(BIND_MW, BIND_MW_TYPE),
HR_IBV_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV),
};
static inline uint32_t to_hr_opcode(enum ibv_wr_opcode ibv_opcode)
{
if (ibv_opcode >= ARRAY_SIZE(hns_roce_opcode))
return HNS_ROCE_WQE_OP_MASK;
return hns_roce_opcode[ibv_opcode];
}
static const unsigned int hns_roce_mtu[] = {
[IBV_MTU_256] = 256,
[IBV_MTU_512] = 512,
[IBV_MTU_1024] = 1024,
[IBV_MTU_2048] = 2048,
[IBV_MTU_4096] = 4096,
};
static inline unsigned int mtu_enum_to_int(enum ibv_mtu mtu)
{
return hns_roce_mtu[mtu];
}
static void *get_send_sge_ex(struct hns_roce_qp *qp, unsigned int n);
static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
const struct ibv_sge *sg)
{
dseg->lkey = htole32(sg->lkey);
dseg->addr = htole64(sg->addr);
dseg->len = htole32(sg->length);
}
static void set_extend_atomic_seg(struct hns_roce_qp *qp, unsigned int sge_cnt,
struct hns_roce_sge_info *sge_info, void *buf)
{
unsigned int sge_mask = qp->ex_sge.sge_cnt - 1;
unsigned int i;
for (i = 0; i < sge_cnt; i++, sge_info->start_idx++)
memcpy(get_send_sge_ex(qp, sge_info->start_idx & sge_mask),
buf + i * HNS_ROCE_SGE_SIZE, HNS_ROCE_SGE_SIZE);
}
static int set_atomic_seg(struct hns_roce_qp *qp, struct ibv_send_wr *wr,
void *dseg, struct hns_roce_sge_info *sge_info)
{
struct hns_roce_wqe_atomic_seg *aseg = dseg;
unsigned int data_len = sge_info->total_len;
uint8_t tmp[ATOMIC_DATA_LEN_MAX] = {};
void *buf[ATOMIC_BUF_NUM_MAX];
unsigned int buf_sge_num;
/* There is only one sge in atomic wr, and data_len is the data length
* in the first sge
*/
if (is_std_atomic(data_len)) {
if (wr->opcode == IBV_WR_ATOMIC_CMP_AND_SWP) {
aseg->fetchadd_swap_data = htole64(wr->wr.atomic.swap);
aseg->cmp_data = htole64(wr->wr.atomic.compare_add);
} else {
aseg->fetchadd_swap_data =
htole64(wr->wr.atomic.compare_add);
aseg->cmp_data = 0;
}
return 0;
}
if (!is_ext_atomic(data_len))
return EINVAL;
buf_sge_num = data_len >> HNS_ROCE_SGE_SHIFT;
aseg->fetchadd_swap_data = 0;
aseg->cmp_data = 0;
/* both ext CAS and ext FAA need 2 bufs */
if ((buf_sge_num << 1) + HNS_ROCE_SGE_IN_WQE > qp->sq.max_gs)
return EINVAL;
if (wr->opcode == IBV_WR_ATOMIC_CMP_AND_SWP) {
buf[0] = (void *)(uintptr_t)wr->wr.atomic.swap;
buf[1] = (void *)(uintptr_t)wr->wr.atomic.compare_add;
} else {
buf[0] = (void *)(uintptr_t)wr->wr.atomic.compare_add;
buf[1] = (void *)(uintptr_t)tmp; /* HW needs all 0 SGEs */
}
if (!buf[0] || !buf[1])
return EINVAL;
set_extend_atomic_seg(qp, buf_sge_num, sge_info, buf[0]);
set_extend_atomic_seg(qp, buf_sge_num, sge_info, buf[1]);
return 0;
}
static enum ibv_wc_status get_wc_status(uint8_t status)
{
static const struct {
unsigned int cqe_status;
enum ibv_wc_status wc_status;
} map[] = {
{ HNS_ROCE_V2_CQE_SUCCESS, IBV_WC_SUCCESS },
{ HNS_ROCE_V2_CQE_LOCAL_LENGTH_ERR, IBV_WC_LOC_LEN_ERR },
{ HNS_ROCE_V2_CQE_LOCAL_QP_OP_ERR, IBV_WC_LOC_QP_OP_ERR },
{ HNS_ROCE_V2_CQE_LOCAL_PROT_ERR, IBV_WC_LOC_PROT_ERR },
{ HNS_ROCE_V2_CQE_WR_FLUSH_ERR, IBV_WC_WR_FLUSH_ERR },
{ HNS_ROCE_V2_CQE_MEM_MANAGERENT_OP_ERR, IBV_WC_MW_BIND_ERR },
{ HNS_ROCE_V2_CQE_BAD_RESP_ERR, IBV_WC_BAD_RESP_ERR },
{ HNS_ROCE_V2_CQE_LOCAL_ACCESS_ERR, IBV_WC_LOC_ACCESS_ERR },
{ HNS_ROCE_V2_CQE_REMOTE_INVAL_REQ_ERR, IBV_WC_REM_INV_REQ_ERR },
{ HNS_ROCE_V2_CQE_REMOTE_ACCESS_ERR, IBV_WC_REM_ACCESS_ERR },
{ HNS_ROCE_V2_CQE_REMOTE_OP_ERR, IBV_WC_REM_OP_ERR },
{ HNS_ROCE_V2_CQE_TRANSPORT_RETRY_EXC_ERR, IBV_WC_RETRY_EXC_ERR },
{ HNS_ROCE_V2_CQE_RNR_RETRY_EXC_ERR, IBV_WC_RNR_RETRY_EXC_ERR },
{ HNS_ROCE_V2_CQE_REMOTE_ABORTED_ERR, IBV_WC_REM_ABORT_ERR },
{ HNS_ROCE_V2_CQE_GENERAL_ERR, IBV_WC_GENERAL_ERR },
{ HNS_ROCE_V2_CQE_XRC_VIOLATION_ERR, IBV_WC_REM_INV_RD_REQ_ERR },
};
for (int i = 0; i < ARRAY_SIZE(map); i++) {
if (status == map[i].cqe_status)
return map[i].wc_status;
}
return IBV_WC_GENERAL_ERR;
}
static struct hns_roce_v2_cqe *get_cqe_v2(struct hns_roce_cq *cq, int entry)
{
return cq->buf.buf + entry * cq->cqe_size;
}
static void *get_sw_cqe_v2(struct hns_roce_cq *cq, int n)
{
struct hns_roce_v2_cqe *cqe = get_cqe_v2(cq, n & cq->verbs_cq.cq.cqe);
return (hr_reg_read(cqe, CQE_OWNER) ^
!!(n & (cq->verbs_cq.cq.cqe + 1))) ? cqe : NULL;
}
static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *cq)
{
return get_sw_cqe_v2(cq, cq->cons_index);
}
static void *get_recv_wqe_v2(struct hns_roce_qp *qp, unsigned int n)
{
return qp->buf.buf + qp->rq.offset + (n << qp->rq.wqe_shift);
}
static void *get_send_wqe(struct hns_roce_qp *qp, unsigned int n)
{
return qp->buf.buf + qp->sq.offset + (n << qp->sq.wqe_shift);
}
static void *get_send_sge_ex(struct hns_roce_qp *qp, unsigned int n)
{
return qp->buf.buf + qp->ex_sge.offset + (n << qp->ex_sge.sge_shift);
}
static void *get_srq_wqe(struct hns_roce_srq *srq, unsigned int n)
{
return srq->wqe_buf.buf + (n << srq->wqe_shift);
}
static void *get_idx_buf(struct hns_roce_idx_que *idx_que, unsigned int n)
{
return idx_que->buf.buf + (n << idx_que->entry_shift);
}
static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, uint16_t ind)
{
uint32_t bitmap_num;
int bit_num;
pthread_spin_lock(&srq->lock);
bitmap_num = ind / BIT_CNT_PER_LONG;
bit_num = ind % BIT_CNT_PER_LONG;
srq->idx_que.bitmap[bitmap_num] |= (1ULL << bit_num);
srq->idx_que.tail++;
pthread_spin_unlock(&srq->lock);
}
static int get_srq_from_cqe(struct hns_roce_v2_cqe *cqe,
struct hns_roce_context *ctx,
struct hns_roce_qp *hr_qp,
struct hns_roce_srq **srq)
{
uint32_t srqn;
if (hr_qp->verbs_qp.qp.qp_type == IBV_QPT_XRC_RECV) {
srqn = hr_reg_read(cqe, CQE_XRC_SRQN);
*srq = hns_roce_find_srq(ctx, srqn);
if (!*srq)
return EINVAL;
} else if (hr_qp->verbs_qp.qp.srq) {
*srq = to_hr_srq(hr_qp->verbs_qp.qp.srq);
}
return 0;
}
static int hns_roce_v2_wq_overflow(struct hns_roce_wq *wq, unsigned int nreq,
struct hns_roce_cq *cq)
{
unsigned int cur;
cur = wq->head - wq->tail;
if (cur + nreq < wq->max_post)
return 0;
pthread_spin_lock(&cq->lock);
cur = wq->head - wq->tail;
pthread_spin_unlock(&cq->lock);
return cur + nreq >= wq->max_post;
}
static void hns_roce_update_rq_db(struct hns_roce_context *ctx,
unsigned int qpn, unsigned int rq_head)
{
struct hns_roce_db rq_db = {};
hr_reg_write(&rq_db, DB_TAG, qpn);
hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB);
hr_reg_write(&rq_db, DB_PI, rq_head);
hns_roce_write64(ctx->uar + ROCEE_VF_DB_CFG0_OFFSET, (__le32 *)&rq_db);
}
static void hns_roce_update_sq_db(struct hns_roce_context *ctx,
struct hns_roce_qp *qp)
{
struct hns_roce_db sq_db = {};
hr_reg_write(&sq_db, DB_TAG, qp->verbs_qp.qp.qp_num);
hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB);
hr_reg_write(&sq_db, DB_PI, qp->sq.head);
hr_reg_write(&sq_db, DB_SL, qp->sl);
hns_roce_write64(qp->sq.db_reg, (__le32 *)&sq_db);
}
static void hns_roce_write512(uint64_t *dest, uint64_t *val)
{
mmio_memcpy_x64(dest, val, sizeof(struct hns_roce_rc_sq_wqe));
}
static void hns_roce_write_dwqe(struct hns_roce_qp *qp, void *wqe)
{
struct hns_roce_rc_sq_wqe *rc_sq_wqe = wqe;
/* All kinds of DirectWQE have the same header field layout */
hr_reg_enable(rc_sq_wqe, RCWQE_FLAG);
hr_reg_write(rc_sq_wqe, RCWQE_DB_SL_L, qp->sl);
hr_reg_write(rc_sq_wqe, RCWQE_DB_SL_H, qp->sl >> HNS_ROCE_SL_SHIFT);
hr_reg_write(rc_sq_wqe, RCWQE_WQE_IDX, qp->sq.head);
hns_roce_write512(qp->sq.db_reg, wqe);
}
static void update_cq_db(struct hns_roce_context *ctx, struct hns_roce_cq *cq)
{
struct hns_roce_db cq_db = {};
hr_reg_write(&cq_db, DB_TAG, cq->cqn);
hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_PTR);
hr_reg_write(&cq_db, DB_CQ_CI, cq->cons_index);
hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1);
hns_roce_write64(ctx->uar + ROCEE_VF_DB_CFG0_OFFSET, (__le32 *)&cq_db);
}
static struct hns_roce_qp *hns_roce_v2_find_qp(struct hns_roce_context *ctx,
uint32_t qpn)
{
uint32_t tind = to_hr_qp_table_index(qpn, ctx);
if (ctx->qp_table[tind].refcnt)
return ctx->qp_table[tind].table[qpn & ctx->qp_table_mask];
else
return NULL;
}
void hns_roce_v2_clear_qp(struct hns_roce_context *ctx, struct hns_roce_qp *qp)
{
uint32_t qpn = qp->verbs_qp.qp.qp_num;
uint32_t tind = to_hr_qp_table_index(qpn, ctx);
pthread_mutex_lock(&ctx->qp_table_mutex);
if (!--ctx->qp_table[tind].refcnt)
free(ctx->qp_table[tind].table);
else if (!--qp->refcnt)
ctx->qp_table[tind].table[qpn & ctx->qp_table_mask] = NULL;
pthread_mutex_unlock(&ctx->qp_table_mutex);
}
static int hns_roce_u_v2_modify_qp(struct ibv_qp *qp, struct ibv_qp_attr *attr,
int attr_mask);
static int hns_roce_flush_cqe(struct hns_roce_qp *hr_qp, uint8_t status)
{
struct ibv_qp_attr attr = {};
int attr_mask;
if (status != HNS_ROCE_V2_CQE_WR_FLUSH_ERR) {
attr_mask = IBV_QP_STATE;
attr.qp_state = IBV_QPS_ERR;
hns_roce_u_v2_modify_qp(&hr_qp->verbs_qp.qp, &attr, attr_mask);
hr_qp->verbs_qp.qp.state = IBV_QPS_ERR;
}
return V2_CQ_OK;
}
static const unsigned int wc_send_op_map[] = {
[HNS_ROCE_SQ_OP_SEND] = IBV_WC_SEND,
[HNS_ROCE_SQ_OP_SEND_WITH_INV] = IBV_WC_SEND,
[HNS_ROCE_SQ_OP_SEND_WITH_IMM] = IBV_WC_SEND,
[HNS_ROCE_SQ_OP_RDMA_WRITE] = IBV_WC_RDMA_WRITE,
[HNS_ROCE_SQ_OP_RDMA_WRITE_WITH_IMM] = IBV_WC_RDMA_WRITE,
[HNS_ROCE_SQ_OP_RDMA_READ] = IBV_WC_RDMA_READ,
[HNS_ROCE_SQ_OP_ATOMIC_COMP_AND_SWAP] = IBV_WC_COMP_SWAP,
[HNS_ROCE_SQ_OP_ATOMIC_FETCH_AND_ADD] = IBV_WC_FETCH_ADD,
[HNS_ROCE_SQ_OP_BIND_MW] = IBV_WC_BIND_MW,
};
static const unsigned int wc_rcv_op_map[] = {
[HNS_ROCE_RECV_OP_RDMA_WRITE_IMM] = IBV_WC_RECV_RDMA_WITH_IMM,
[HNS_ROCE_RECV_OP_SEND] = IBV_WC_RECV,
[HNS_ROCE_RECV_OP_SEND_WITH_IMM] = IBV_WC_RECV,
[HNS_ROCE_RECV_OP_SEND_WITH_INV] = IBV_WC_RECV,
};
static void get_opcode_for_resp(struct hns_roce_v2_cqe *cqe, struct ibv_wc *wc,
uint32_t opcode)
{
switch (opcode) {
case HNS_ROCE_RECV_OP_SEND:
wc->wc_flags = 0;
break;
case HNS_ROCE_RECV_OP_SEND_WITH_INV:
wc->wc_flags = IBV_WC_WITH_INV;
wc->invalidated_rkey = le32toh(cqe->rkey);
break;
case HNS_ROCE_RECV_OP_RDMA_WRITE_IMM:
case HNS_ROCE_RECV_OP_SEND_WITH_IMM:
wc->wc_flags = IBV_WC_WITH_IMM;
wc->imm_data = htobe32(le32toh(cqe->immtdata));
break;
default:
return;
}
wc->opcode = wc_rcv_op_map[opcode];
}
static void handle_recv_inl_data(struct hns_roce_v2_cqe *cqe,
struct hns_roce_rinl_buf *rinl_buf,
uint32_t wr_cnt, uint8_t *buf)
{
struct ibv_sge *sge_list;
uint32_t sge_num, data_len;
uint32_t sge_cnt, size;
sge_list = rinl_buf->wqe_list[wr_cnt].sg_list;
sge_num = rinl_buf->wqe_list[wr_cnt].sge_cnt;
data_len = le32toh(cqe->byte_cnt);
for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
size = min(sge_list[sge_cnt].length, data_len);
memcpy((void *)(uintptr_t)sge_list[sge_cnt].addr, (void *)buf, size);
data_len -= size;
buf += size;
}
if (data_len)
hr_reg_write(cqe, CQE_STATUS, HNS_ROCE_V2_CQE_LOCAL_LENGTH_ERR);
}
static void handle_recv_cqe_inl_from_rq(struct hns_roce_v2_cqe *cqe,
struct hns_roce_qp *cur_qp)
{
uint32_t wr_num;
wr_num = hr_reg_read(cqe, CQE_WQE_IDX) & (cur_qp->rq.wqe_cnt - 1);
handle_recv_inl_data(cqe, &cur_qp->rq_rinl_buf, wr_num,
(uint8_t *)cqe->payload);
}
static void handle_recv_cqe_inl_from_srq(struct hns_roce_v2_cqe *cqe,
struct hns_roce_srq *srq)
{
uint32_t wr_num;
wr_num = hr_reg_read(cqe, CQE_WQE_IDX) & (srq->wqe_cnt - 1);
handle_recv_inl_data(cqe, &srq->srq_rinl_buf, wr_num,
(uint8_t *)cqe->payload);
}
static void handle_recv_rq_inl(struct hns_roce_v2_cqe *cqe,
struct hns_roce_qp *cur_qp)
{
uint8_t *wqe_buf;
uint32_t wr_num;
wr_num = hr_reg_read(cqe, CQE_WQE_IDX) & (cur_qp->rq.wqe_cnt - 1);
wqe_buf = (uint8_t *)get_recv_wqe_v2(cur_qp, wr_num);
handle_recv_inl_data(cqe, &cur_qp->rq_rinl_buf, wr_num, wqe_buf);
}
static const uint8_t pktype_for_ud[] = {
HNS_ROCE_PKTYPE_ROCE_V1,
HNS_ROCE_PKTYPE_ROCE_V2_IPV4,
HNS_ROCE_PKTYPE_ROCE_V2_IPV6
};
static void parse_for_ud_qp(struct hns_roce_v2_cqe *cqe, struct ibv_wc *wc)
{
uint8_t port_type = hr_reg_read(cqe, CQE_PORT_TYPE);
wc->sl = pktype_for_ud[port_type];
wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN);
wc->slid = 0;
wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IBV_WC_GRH : 0;
wc->pkey_index = 0;
}
static void parse_cqe_for_srq(struct hns_roce_v2_cqe *cqe, struct ibv_wc *wc,
struct hns_roce_srq *srq)
{
uint32_t wqe_idx;
wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX);
wc->wr_id = srq->wrid[wqe_idx & (srq->wqe_cnt - 1)];
hns_roce_free_srq_wqe(srq, wqe_idx);
if (hr_reg_read(cqe, CQE_CQE_INLINE))
handle_recv_cqe_inl_from_srq(cqe, srq);
}
static int parse_cqe_for_resp(struct hns_roce_v2_cqe *cqe, struct ibv_wc *wc,
struct hns_roce_qp *hr_qp)
{
struct hns_roce_wq *wq;
wq = &hr_qp->rq;
wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
++wq->tail;
if (hr_qp->verbs_qp.qp.qp_type == IBV_QPT_UD)
parse_for_ud_qp(cqe, wc);
if (hr_reg_read(cqe, CQE_CQE_INLINE))
handle_recv_cqe_inl_from_rq(cqe, hr_qp);
else if (hr_reg_read(cqe, CQE_RQ_INLINE))
handle_recv_rq_inl(cqe, hr_qp);
return 0;
}
static void parse_cqe_for_req(struct hns_roce_v2_cqe *cqe, struct ibv_wc *wc,
struct hns_roce_qp *hr_qp, uint8_t opcode)
{
struct hns_roce_wq *wq;
uint32_t wqe_idx;
wq = &hr_qp->sq;
/*
* in case of signalling, the tail pointer needs to be updated
* according to the wqe idx in the current cqe first
*/
if (hr_qp->sq_signal_bits) {
wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX);
/* get the processed wqes num since last signalling */
wq->tail += (wqe_idx - wq->tail) & (wq->wqe_cnt - 1);
}
/* write the wr_id of wq into the wc */
wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
++wq->tail;
switch (opcode) {
case HNS_ROCE_SQ_OP_SEND:
case HNS_ROCE_SQ_OP_SEND_WITH_INV:
case HNS_ROCE_SQ_OP_RDMA_WRITE:
case HNS_ROCE_SQ_OP_BIND_MW:
wc->wc_flags = 0;
break;
case HNS_ROCE_SQ_OP_SEND_WITH_IMM:
case HNS_ROCE_SQ_OP_RDMA_WRITE_WITH_IMM:
wc->wc_flags = IBV_WC_WITH_IMM;
break;
case HNS_ROCE_SQ_OP_RDMA_READ:
case HNS_ROCE_SQ_OP_ATOMIC_COMP_AND_SWAP:
case HNS_ROCE_SQ_OP_ATOMIC_FETCH_AND_ADD:
wc->wc_flags = 0;
wc->byte_len = le32toh(cqe->byte_cnt);
break;
default:
wc->wc_flags = 0;
return;
}
wc->opcode = wc_send_op_map[opcode];
}
static void cqe_proc_sq(struct hns_roce_qp *hr_qp, uint32_t wqe_idx,
struct hns_roce_cq *cq)
{
struct hns_roce_wq *wq = &hr_qp->sq;
if (hr_qp->sq_signal_bits)
wq->tail += (wqe_idx - wq->tail) & (wq->wqe_cnt - 1);
cq->verbs_cq.cq_ex.wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
++wq->tail;
}
static void cqe_proc_srq(struct hns_roce_srq *srq, uint32_t wqe_idx,
struct hns_roce_cq *cq)
{
cq->verbs_cq.cq_ex.wr_id = srq->wrid[wqe_idx & (srq->wqe_cnt - 1)];
hns_roce_free_srq_wqe(srq, wqe_idx);
if (hr_reg_read(cq->cqe, CQE_CQE_INLINE))
handle_recv_cqe_inl_from_srq(cq->cqe, srq);
}
static void cqe_proc_rq(struct hns_roce_qp *hr_qp, struct hns_roce_cq *cq)
{
struct hns_roce_wq *wq = &hr_qp->rq;
cq->verbs_cq.cq_ex.wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
++wq->tail;
if (hr_reg_read(cq->cqe, CQE_CQE_INLINE))
handle_recv_cqe_inl_from_rq(cq->cqe, hr_qp);
else if (hr_reg_read(cq->cqe, CQE_RQ_INLINE))
handle_recv_rq_inl(cq->cqe, hr_qp);
}
static int cqe_proc_wq(struct hns_roce_context *ctx, struct hns_roce_qp *qp,
struct hns_roce_cq *cq)
{
struct hns_roce_v2_cqe *cqe = cq->cqe;
struct hns_roce_srq *srq = NULL;
uint32_t wqe_idx;
wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX);
if (hr_reg_read(cqe, CQE_S_R) == CQE_FOR_SQ) {
cqe_proc_sq(qp, wqe_idx, cq);
} else {
if (get_srq_from_cqe(cqe, ctx, qp, &srq))
return V2_CQ_POLL_ERR;
if (srq)
cqe_proc_srq(srq, wqe_idx, cq);
else
cqe_proc_rq(qp, cq);
}
return 0;
}
static int parse_cqe_for_cq(struct hns_roce_context *ctx, struct hns_roce_cq *cq,
struct hns_roce_qp *cur_qp, struct ibv_wc *wc)
{
struct hns_roce_v2_cqe *cqe = cq->cqe;
struct hns_roce_srq *srq = NULL;
uint8_t opcode;
if (!wc) {
if (cqe_proc_wq(ctx, cur_qp, cq))
return V2_CQ_POLL_ERR;
return 0;
}
opcode = hr_reg_read(cqe, CQE_OPCODE);
if (hr_reg_read(cqe, CQE_S_R) == CQE_FOR_SQ) {
parse_cqe_for_req(cqe, wc, cur_qp, opcode);
} else {
wc->byte_len = le32toh(cqe->byte_cnt);
get_opcode_for_resp(cqe, wc, opcode);
if (get_srq_from_cqe(cqe, ctx, cur_qp, &srq))
return V2_CQ_POLL_ERR;
if (srq)
parse_cqe_for_srq(cqe, wc, srq);
else
parse_cqe_for_resp(cqe, wc, cur_qp);
}
return 0;
}
static int hns_roce_poll_one(struct hns_roce_context *ctx,
struct hns_roce_qp **cur_qp, struct hns_roce_cq *cq,
struct ibv_wc *wc)
{
struct hns_roce_v2_cqe *cqe;
uint8_t status, wc_status;
uint32_t qpn;
cqe = next_cqe_sw_v2(cq);
if (!cqe)
return wc ? V2_CQ_EMPTY : ENOENT;
cq->cqe = cqe;
++cq->cons_index;
udma_from_device_barrier();
qpn = hr_reg_read(cqe, CQE_LCL_QPN);
/* if cur qp is null, then could not get the correct qpn */
if (!*cur_qp || qpn != (*cur_qp)->verbs_qp.qp.qp_num) {
*cur_qp = hns_roce_v2_find_qp(ctx, qpn);
if (!*cur_qp)
return V2_CQ_POLL_ERR;
}
if (parse_cqe_for_cq(ctx, cq, *cur_qp, wc))
return V2_CQ_POLL_ERR;
status = hr_reg_read(cqe, CQE_STATUS);
wc_status = get_wc_status(status);
if (wc) {
wc->status = wc_status;
wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS);
wc->qp_num = qpn;
} else {
cq->verbs_cq.cq_ex.status = wc_status;
}
if (status == HNS_ROCE_V2_CQE_SUCCESS ||
status == HNS_ROCE_V2_CQE_GENERAL_ERR)
return V2_CQ_OK;
/*
* once a cqe in error status, the driver needs to help the HW to
* generated flushed cqes for all subsequent wqes
*/
return hns_roce_flush_cqe(*cur_qp, status);
}
static int hns_roce_u_v2_poll_cq(struct ibv_cq *ibvcq, int ne,
struct ibv_wc *wc)
{
struct hns_roce_context *ctx = to_hr_ctx(ibvcq->context);
struct hns_roce_cq *cq = to_hr_cq(ibvcq);
struct hns_roce_qp *qp = NULL;
int err = V2_CQ_OK;
int npolled;
pthread_spin_lock(&cq->lock);
for (npolled = 0; npolled < ne; ++npolled) {
err = hns_roce_poll_one(ctx, &qp, cq, wc + npolled);
if (err != V2_CQ_OK)
break;
}
if (npolled || err == V2_CQ_POLL_ERR) {
if (cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)
*cq->db = cq->cons_index & RECORD_DB_CI_MASK;
else
update_cq_db(ctx, cq);
}
pthread_spin_unlock(&cq->lock);
return err == V2_CQ_POLL_ERR ? err : npolled;
}
static int hns_roce_u_v2_arm_cq(struct ibv_cq *ibvcq, int solicited)
{
struct hns_roce_context *ctx = to_hr_ctx(ibvcq->context);
struct hns_roce_cq *cq = to_hr_cq(ibvcq);
struct hns_roce_db cq_db = {};
uint32_t solicited_flag;
uint32_t ci;
ci = cq->cons_index & ((cq->cq_depth << 1) - 1);
solicited_flag = solicited ? HNS_ROCE_V2_CQ_DB_REQ_SOL :
HNS_ROCE_V2_CQ_DB_REQ_NEXT;
hr_reg_write(&cq_db, DB_TAG, cq->cqn);
hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NTR);
hr_reg_write(&cq_db, DB_CQ_CI, ci);
hr_reg_write(&cq_db, DB_CQ_CMD_SN, cq->arm_sn);
hr_reg_write(&cq_db, DB_CQ_NOTIFY, solicited_flag);
hns_roce_write64(ctx->uar + ROCEE_VF_DB_CFG0_OFFSET, (__le32 *)&cq_db);
return 0;
}
static inline int check_qp_send(struct ibv_qp *qp)
{
if (unlikely(qp->state == IBV_QPS_RESET ||
qp->state == IBV_QPS_INIT ||
qp->state == IBV_QPS_RTR))
return EINVAL;
return 0;
}
static void set_rc_sge(struct hns_roce_v2_wqe_data_seg *dseg,
struct hns_roce_qp *qp, struct ibv_send_wr *wr,
struct hns_roce_sge_info *sge_info)
{
uint32_t mask = qp->ex_sge.sge_cnt - 1;
uint32_t index = sge_info->start_idx;
struct ibv_sge *sge = wr->sg_list;
int total_sge = wr->num_sge;
bool flag = false;
uint32_t len = 0;
uint32_t cnt = 0;
int i;
if (wr->opcode == IBV_WR_ATOMIC_FETCH_AND_ADD ||
wr->opcode == IBV_WR_ATOMIC_CMP_AND_SWP)
total_sge = 1;
else
flag = !!(wr->send_flags & IBV_SEND_INLINE);
for (i = 0; i < total_sge; i++, sge++) {
if (unlikely(!sge->length))
continue;
len += sge->length;
cnt++;
if (flag)
continue;
if (cnt <= HNS_ROCE_SGE_IN_WQE) {
set_data_seg_v2(dseg, sge);
dseg++;
} else {
dseg = get_send_sge_ex(qp, index & mask);
set_data_seg_v2(dseg, sge);
index++;
}
}
sge_info->start_idx = index;
sge_info->valid_num = cnt;
sge_info->total_len = len;
}
static void set_ud_sge(struct hns_roce_v2_wqe_data_seg *dseg,
struct hns_roce_qp *qp, struct ibv_send_wr *wr,
struct hns_roce_sge_info *sge_info)
{
int flag = wr->send_flags & IBV_SEND_INLINE;
uint32_t mask = qp->ex_sge.sge_cnt - 1;
uint32_t index = sge_info->start_idx;
struct ibv_sge *sge = wr->sg_list;
uint32_t len = 0;
uint32_t cnt = 0;
int i;
for (i = 0; i < wr->num_sge; i++, sge++) {
if (unlikely(!sge->length))
continue;
len += sge->length;
cnt++;
if (flag)
continue;
/* No inner sge in UD wqe */
dseg = get_send_sge_ex(qp, index & mask);
set_data_seg_v2(dseg, sge);
index++;
}
sge_info->start_idx = index;
sge_info->valid_num = cnt;
sge_info->total_len = len;
}
static void get_src_buf_info(void **src_addr, uint32_t *src_len,
const void *buf_list, int buf_idx,
enum hns_roce_wr_buf_type type)
{
if (type == WR_BUF_TYPE_POST_SEND) {
const struct ibv_sge *sg_list = buf_list;
*src_addr = (void *)(uintptr_t)sg_list[buf_idx].addr;
*src_len = sg_list[buf_idx].length;
} else {
const struct ibv_data_buf *bf_list = buf_list;
*src_addr = bf_list[buf_idx].addr;
*src_len = bf_list[buf_idx].length;
}
}
static int fill_ext_sge_inl_data(struct hns_roce_qp *qp,
struct hns_roce_sge_info *sge_info,
const void *buf_list,
uint32_t num_buf,
enum hns_roce_wr_buf_type buf_type)
{
unsigned int sge_mask = qp->ex_sge.sge_cnt - 1;
void *dst_addr, *src_addr, *tail_bound_addr;
uint32_t src_len, tail_len;
int i;
if (sge_info->total_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE)
return EINVAL;
dst_addr = get_send_sge_ex(qp, sge_info->start_idx & sge_mask);
tail_bound_addr = get_send_sge_ex(qp, qp->ex_sge.sge_cnt);
for (i = 0; i < num_buf; i++) {
tail_len = (uintptr_t)tail_bound_addr - (uintptr_t)dst_addr;
get_src_buf_info(&src_addr, &src_len, buf_list, i, buf_type);
if (src_len < tail_len) {
memcpy(dst_addr, src_addr, src_len);
dst_addr += src_len;
} else if (src_len == tail_len) {
memcpy(dst_addr, src_addr, src_len);
dst_addr = get_send_sge_ex(qp, 0);
} else {
memcpy(dst_addr, src_addr, tail_len);
dst_addr = get_send_sge_ex(qp, 0);
src_addr += tail_len;
src_len -= tail_len;
memcpy(dst_addr, src_addr, src_len);
dst_addr += src_len;
}
}
sge_info->valid_num = DIV_ROUND_UP(sge_info->total_len, HNS_ROCE_SGE_SIZE);
sge_info->start_idx += sge_info->valid_num;
return 0;
}
static void set_ud_inl_seg(struct hns_roce_ud_sq_wqe *ud_sq_wqe,
uint8_t *data)
{
uint32_t *loc = (uint32_t *)data;
uint32_t tmp_data;
hr_reg_write(ud_sq_wqe, UDWQE_INLINE_DATA_15_0, *loc & 0xffff);
hr_reg_write(ud_sq_wqe, UDWQE_INLINE_DATA_23_16, (*loc >> 16) & 0xff);
tmp_data = *loc >> 24;
loc++;
tmp_data |= ((*loc & 0xffff) << 8);
hr_reg_write(ud_sq_wqe, UDWQE_INLINE_DATA_47_24, tmp_data);
hr_reg_write(ud_sq_wqe, UDWQE_INLINE_DATA_63_48, *loc >> 16);
}
static void fill_ud_inn_inl_data(const struct ibv_send_wr *wr,
struct hns_roce_ud_sq_wqe *ud_sq_wqe)
{
uint8_t data[HNS_ROCE_MAX_UD_INL_INN_SZ] = {};
void *tmp = data;
int i;
for (i = 0; i < wr->num_sge; i++) {
memcpy(tmp, (void *)(uintptr_t)wr->sg_list[i].addr,
wr->sg_list[i].length);
tmp += wr->sg_list[i].length;
}
set_ud_inl_seg(ud_sq_wqe, data);
}
static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len)
{
int mtu = mtu_enum_to_int(qp->path_mtu);
return (len <= qp->max_inline_data && len <= mtu);
}
static int set_ud_inl(struct hns_roce_qp *qp, const struct ibv_send_wr *wr,
struct hns_roce_ud_sq_wqe *ud_sq_wqe,
struct hns_roce_sge_info *sge_info)
{
int ret;
if (!check_inl_data_len(qp, sge_info->total_len))
return EINVAL;
if (sge_info->total_len <= HNS_ROCE_MAX_UD_INL_INN_SZ) {
hr_reg_clear(ud_sq_wqe, UDWQE_INLINE_TYPE);
fill_ud_inn_inl_data(wr, ud_sq_wqe);
} else {
hr_reg_enable(ud_sq_wqe, UDWQE_INLINE_TYPE);
ret = fill_ext_sge_inl_data(qp, sge_info,
wr->sg_list, wr->num_sge,
WR_BUF_TYPE_POST_SEND);
if (ret)
return ret;
hr_reg_write(ud_sq_wqe, UDWQE_SGE_NUM, sge_info->valid_num);
}
return 0;
}
static __le32 get_immtdata(enum ibv_wr_opcode opcode, const struct ibv_send_wr *wr)
{
switch (opcode) {
case IBV_WR_SEND_WITH_IMM:
case IBV_WR_RDMA_WRITE_WITH_IMM:
return htole32(be32toh(wr->imm_data));
default:
return 0;
}
}
static int check_ud_opcode(struct hns_roce_ud_sq_wqe *ud_sq_wqe,
const struct ibv_send_wr *wr)
{
uint32_t ib_op = wr->opcode;