Skip to content

Commit

Permalink
riscv: dts: starfive: visionfive-2: Fix lower rate of CPUfreq by sett…
Browse files Browse the repository at this point in the history
…ing PLL0 rate to 1.5GHz

CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz.
But now PLL0 rate is 1GHz and the cpu frequency loads become
333/500/500/1000MHz in fact.

So PLL0 rate should be default set to 1.5GHz and set the
cpu_core rate to 500MHz in safe.

Fixes: e2c510d ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
  • Loading branch information
SFxingyuwu authored and Björn Töpel committed Apr 10, 2024
1 parent fe46509 commit 06b9411
Showing 1 changed file with 6 additions and 0 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -390,6 +390,12 @@
};
};

&syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
<&pllclk JH7110_PLLCLK_PLL0_OUT>;
assigned-clock-rates = <500000000>, <1500000000>;
};

&sysgpio {
i2c0_pins: i2c0-0 {
i2c-pins {
Expand Down

0 comments on commit 06b9411

Please sign in to comment.