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riscv: Add remaining module relocations and tests #139
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With the C-extension regular 32bit instructions are not necessarily aligned on 4-byte boundaries. RISC-V instructions are in fact an ordered list of 16bit little-endian "parcels", so access the instruction as such. This should also make the code work in case someone builds a big-endian RISC-V machine. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Add all final module relocations and add error logs explaining the ones that are not supported. Implement overflow checks for ADD/SUB/SET/ULEB128 relocations. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Add test cases for the two main groups of relocations added: SUB and SET, along with uleb128. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
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At least one diff in series https://patchwork.kernel.org/project/linux-riscv/list/?series=798236 irrelevant now. Closing PR. |
Pull request for series with
subject: riscv: Add remaining module relocations and tests
version: 3
url: https://patchwork.kernel.org/project/linux-riscv/list/?series=793649